SSTUB32866BHLFT IDT, Integrated Device Technology Inc, SSTUB32866BHLFT Datasheet - Page 10

• Manufacturer Part Number: SSTUB32866BHLFT
• Description: IC REGIST BUFF 25BIT DDR2 96-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTUB32866BHLFT

• Number Of Bits: 25, 14
• Logic Type: 1:1, 1:2 Configurable Registered Buffer with Parity
• Supply Voltage: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 96-BGA
• Logic Family: SSTU
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Inputs: 25
• Number Of Outputs: 25
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 410(Min)MHz
• Mounting: Surface Mount
• Pin Count: 96
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2. Device standard (cont'd)
1165A—3/21/07
†
‡
After RST is switched from low to high, all data and PAR_IN inputs signals must be set and held low for a minimum time of t
max, to avoid false error.
If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+2 clock pulse, and it will be valid on
the n+3 clock pulse.
D1•D25 †
PAR_IN †
Q1•Q25
QERR ‡
PPO
DCS
RST
CSR
CK
CK
Figure 9 — Timing diagram for SSTU32866 used as a single device; C0=0, C1=0;
t act
t pdm , t pdmss
RST Switches from L to H
n
t su
H, L, or X
CK to Q
Data to QERR Latency
CK to QERR
n + 1
t su
10
t PHL
t h
n + 2
CK to PPO
t h
t pd
Advance Information
H or L
CK to QERR
n + 3
t PHL , t PLH
ICSSSTUB32866B
n + 4
ACT