SSTUB32866BHLFT IDT, Integrated Device Technology Inc, SSTUB32866BHLFT Datasheet - Page 14

• Manufacturer Part Number: SSTUB32866BHLFT
• Description: IC REGIST BUFF 25BIT DDR2 96-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTUB32866BHLFT

• Number Of Bits: 25, 14
• Logic Type: 1:1, 1:2 Configurable Registered Buffer with Parity
• Supply Voltage: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 96-BGA
• Logic Family: SSTU
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Inputs: 25
• Number Of Outputs: 25
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 410(Min)MHz
• Mounting: Surface Mount
• Pin Count: 96
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2. Device standard (cont'd)
1165A—3/21/07
†
Figure 13 — Timing diagram for the first SSTU32866 (1:2 register-A configuration) device used in
(not used)
If the data is clocked in on the clock pulse, the QERR output signal will be generated on the n+1 clock pulse, and it will be valid on
the n+2 clock pulse. If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or
until RST is driven low.
Q1•Q14
D1•D14
PAR_IN
QERR †
PPO
DCS
RST
CSR
CK
CK
Unknown input
event
t pdm , t pdmss
pair; C0=0, C1=1; RST being held high
t su
CK to Q
n
t su
Output signal is dependent on
the prior unknown input event
Data to PPO
Data to QERR
Latency
t h
Latency
CK to PPO
n + 1
14
t pd
t h
n + 2
Advance Information
CK to QERR
t PHL or t PLH
n + 3
ICSSSTUB32866B
n + 4
H or L