MAX11642EEG+T Maxim Integrated, MAX11642EEG+T Datasheet
MAX11642EEG+T
Specifications of MAX11642EEG+T
Related parts for MAX11642EEG+T
MAX11642EEG+T Summary of contents
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... PART OF VOLTAGE INPUTS RANGE (V) MAX11638EEE+T 8 4.75 to 5.25 MAX11639EEE+T 8 2.7 to 3.6 MAX11642EEG+T 16 4.75 to 5.25 MAX11643EEG+T 16 2.7 to 3.6 Note: All devices are specified over the -40°C to +85°C operating temperature range. + Denotes a lead(Pb)-free/RoHS-compliant package Tape and reel. AutoShutdown is a trademark of Maxim Integrated Products, Inc. QSPI is a trademark of Motorola, Inc. ...
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ADCs with FIFO and Internal Reference ABSOLUTE MAXIMUM RATINGS V to GND ..............................................................-0.3V to +6V DD CS, SCLK, DIN, EOC, DOUT to GND.........-0. AIN0–AIN13, CNVST/AIN_, REF to GND ...........................................-0. Maximum Current into Any ...
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ADCs ELECTRICAL CHARACTERISTICS (continued +2.7V to +3.6V (MAX11639/MAX11643 4.8MHz (external clock 50% duty cycle unless otherwise noted. Typical values are at T MAX PARAMETER SYMBOL CONVERSION RATE Power-Up Time Acquisition ...
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ADCs with FIFO and Internal Reference ELECTRICAL CHARACTERISTICS (continued +2.7V to +3.6V (MAX11639/MAX11643 4.8MHz (external clock 50% duty cycle unless otherwise noted. Typical values are at T MAX PARAMETER SYMBOL ...
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ADCs TIMING CHARACTERISTICS (V = +2.7V to +3.6V (MAX11639/MAX11643 4.8MHz (external clock 50% duty cycle unless otherwise noted. Typical values are at T MAX PARAMETER SYMBOL SCLK Clock Period SCLK Pulse-Width High ...
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ADCs with FIFO and Internal Reference ( and V = 2.5V (MAX11639/MAX11643 REF C = 30pF 300ksps +25°C, unless otherwise noted.) LOAD SAMPLE A DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE ...
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ADCs ( and V = 2.5V (MAX11639/MAX11643 REF C = 30pF 300ksps, T LOAD SAMPLE A SUPPLY CURRENT vs. SUPPLY VOLTAGE 2000 INTERNAL 1800 REFERENCE 1600 1400 1200 EXTERNAL REFERENCE 1000 ...
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ADCs with FIFO and Internal Reference ( and V = 2.5V (MAX11639/MAX11643 REF C = 30pF 300ksps +25°C, unless otherwise noted.) LOAD SAMPLE A INTERNAL REFERENCE VOLTAGE vs. SUPPLY ...
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ADCs ( and V = 2.5V (MAX11639/MAX11643 REF C = 30pF 300ksps, T LOAD SAMPLE A OFFSET ERROR vs. TEMPERATURE 0.8 MAX11638/MAX11642 0.4 0 -40 - TEMPERATURE (°C) ...
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ADCs with FIFO and Internal Reference MAX11638 MAX11642 MAX11639 MAX11643 (8 CHANNELS) (16 CHANNELS) 1–7 — — 1–15 8 — — ...
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ADCs CS t CSS0 t CL SCLK DIN t DOE DOUT Figure 1. Detailed Serial-Interface Timing Diagram CS DIN SCLK CNVST AIN0 AIN1 AIN15 REF Figure 2. Functional Diagram Detailed Description The MAX11638/MAX11639/MAX11642/MAX11643 ...
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ADCs with FIFO and Internal Reference Converter Operation The MAX11638/MAX11639/MAX11642/MAX11643 ADCs use a successive-approximation register (SAR) conver- sion technique and an on-chip T/H block to convert voltage signals into an 8-bit digital result. This single- ended configuration ...
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ADCs True Differential Analog Input T/H The equivalent circuit of Figure 3 shows the MAX11638/MAX11639/MAX11642/MAX11643’s input architecture. In track mode, a positive input capacitor is connected to AIN0–AIN15. A negative input capacitor is connected to GND. For ...
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ADCs with FIFO and Internal Reference Conversion Register Select active analog input channels per scan and scan modes by writing to the conversion register. Table 2 details channel selection and the four scan modes. Request a scan ...
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ADCs Table 3. Setup Register* BIT NAME BIT — 7 (MSB) Set to zero to select setup register. — 6 Set select setup register. Clock mode and CNVST configuration. Resets power-up. ...
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ADCs with FIFO and Internal Reference Table 4. Averaging Register* BIT NAME BIT — 7 (MSB) Set to zero to select averaging register. — 6 Set to zero to select averaging register. — 5 Set to 1 ...
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ADCs Power-Up Default State The MAX11638/MAX11639/MAX11642/MAX11643 power up with all blocks in shutdown, including the ref- erence. All registers power up in state 00000000, except for the setup register, which powers up in clock mode 10 (CKSEL1 ...
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ADCs with FIFO and Internal Reference CNVST (ACQUISITION1) (ACQUISITION2) CS (CONVERSION1) SCLK DOUT EOC REQUEST MULTIPLE CONVERSIONS BY SETTING CNVST LOW FOR EACH CONVERSION. Figure 5. Clock Mode 01 (CONVERSION BYTE) DIN CS SCLK DOUT EOC THE ...
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ADCs DIN (ACQUISITION1) CS SCLK DOUT EOC EXTERNALLY TIMED ACQUISITION, SAMPLING AND CONVERSION WITHOUT CNVST. Figure 7. Clock Mode 11 Initiate a conversion by writing a byte to the conversion register followed by 16 SCLK cycles. If ...
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ADCs with FIFO and Internal Reference Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a ...
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ADCs with FIFO and Internal Reference Pin Configurations (continued) TOP VIEW + AIN0 1 24 EOC AIN1 2 23 DOUT AIN2 3 22 DIN AIN3 4 21 SCLK MAX11642 AIN4 MAX11643 AIN5 6 19 ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2011 Maxim Integrated Products DESCRIPTION Maxim is a registered trademark of Maxim Integrated Products, Inc ...