MAX11642EEG+T Maxim Integrated, MAX11642EEG+T Datasheet - Page 19

• Manufacturer Part Number: MAX11642EEG+T
• Description: Analog to Digital Converters - ADC 16Ch 8-Bit 300ksps w/FIFO & Int Ref
• Manufacturer: Maxim Integrated

Specifications of MAX11642EEG+T

• Rohs: yes
• Number Of Channels: 16/8
• Architecture: SAR
• Conversion Rate: 300 KSPs
• Resolution: 8 bit
• Input Type: Single-Ended/Differential
• Interface Type: SPI
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Power Dissipation: 762 mW
• Number Of Converters: 1
• Voltage Reference: 4.096 V

Figure 7. Clock Mode 11
Initiate a conversion by writing a byte to the conversion
register followed by 16 SCLK cycles. If CS is pulsed
high between the 8th and 9th cycles, the pulse width
must be less than 100µs. To continuously convert at 16
cycles per conversion, alternate 1 byte of zeros
between each conversion byte.
If reference mode 00 is requested, wait 65µs with CS
high after writing the conversion byte to extend the
acquisition and allow the internal reference to power up.
If the first byte of an entry in the FIFO is partially read
(CS is pulled high after fewer than eight SCLK cycles),
the second byte of data that is read out contains the
next 8 bits (not b7–b0). The remaining bits are lost for
that entry. If the first byte of an entry in the FIFO is read
out fully, but the second byte is read out partially, the
rest of the entry is lost. The remaining data in the FIFO
is uncorrupted and can be read out normally after tak-
ing CS low again, as long as the 4 leading bits (normal-
ly zeros) are ignored. Internal registers that are written
partially through the SPI contain new values, starting at
the MSB up to the point that the partial write is stopped.
The part of the register that is not written contains previ-
ously written values. If CS is pulled low before EOC
goes low, a conversion cannot be completed and the
FIFO is corrupted.
Figure 8 shows the unipolar transfer function for single-
ended inputs. Code transitions occur halfway between
successive-integer LSB values. Output coding is binary,
with 1 LSB = V
DIN
SCLK
DOUT
EOC
CS
EXTERNALLY TIMED ACQUISITION, SAMPLING AND CONVERSION WITHOUT CNVST.
Partial Reads and Partial Writes
REF
/256.
______________________________________________________________________________________
(ACQUISITION1)
8-Bit, 16-/8-Channel, 300ksps ADCs
Transfer Function
with FIFO and Internal Reference
(CONVERSION BYTE)
MSB1
(CONVERSION1)
Figure 8. Unipolar Transfer Function, Full Scale (FS) = V
Use PCBs for best performance. Do not use wire-
wrapped boards. Board layout should ensure that digi-
tal and analog signal lines are separated from each
other. Do not run analog and digital (especially clock)
signals parallel to one another or run digital lines under-
neath the package. High-frequency noise in the V
power supply can affect performance. Bypass the V
supply with a 0.1µF capacitor to GND, close to the V
pin. Minimize capacitor lead lengths for best supply-
noise rejection. If the power supply is very noisy, con-
nect a 10Ω resistor in series with the supply to improve
power-supply filtering.
11 . . .
11 . . .
11 . . .
00 . . .
00 . . .
00 . . .
00 . . .
. . . 111
. . . 110
. . . 101
. . . 011
. . . 010
. . . 001
. . . 000
OUTPUT CODE
LSB1
(COM)
Layout, Grounding, and Bypassing
0
1
2
INPUT VOLTAGE (LSB)
(ACQUISITION2)
3
FULL-SCALE
TRANSITION
FS - 3/2 LSB
MSB2
1 LSB =
FS = V
ZS = V
FS
REF
COM
V
256
REF
+ V
REF
COM
DD
DD
DD
19