MAX11642EEG+T Maxim Integrated, MAX11642EEG+T Datasheet - Page 13

• Manufacturer Part Number: MAX11642EEG+T
• Description: Analog to Digital Converters - ADC 16Ch 8-Bit 300ksps w/FIFO & Int Ref
• Manufacturer: Maxim Integrated

Specifications of MAX11642EEG+T

• Rohs: yes
• Number Of Channels: 16/8
• Architecture: SAR
• Conversion Rate: 300 KSPs
• Resolution: 8 bit
• Input Type: Single-Ended/Differential
• Interface Type: SPI
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Power Dissipation: 762 mW
• Number Of Converters: 1
• Voltage Reference: 4.096 V

The equivalent circuit of Figure 3 shows the
MAX11638/MAX11639/MAX11642/MAX11643’s input
architecture. In track mode, a positive input capacitor is
connected to AIN0–AIN15. A negative input capacitor is
connected to GND. For external T/H timing, use clock
mode 01. After the T/H enters hold mode, the difference
between the sampled positive and negative input volt-
ages is converted. The time required for the T/H to
acquire an input signal is determined by how quickly its
input capacitance is charged. If the input signal’s
source impedance is high, the required acquisition time
lengthens. The acquisition time, t
time needed for a signal to be acquired, plus the power-
up time. It is calculated by the following equation:
where R
input signal, and t
device. The varying power-up times are detailed in the
explanation of the clock mode conversions. When the
conversion is internally timed, t
1.4µs, and any source impedance below 300Ω does not
significantly affect the ADC’s AC performance. A high-
impedance source can be accommodated either by
lengthening t
the positive and negative analog inputs.
The MAX11638/MAX11639/MAX11642/MAX11643 con-
tain a FIFO buffer that can hold up to 16 ADC results.
This allows the ADC to handle multiple internally clocked
conversions, without tying up the serial bus. If the FIFO is
filled and further conversions are requested without
reading from the FIFO, the oldest ADC results are over-
written by the new ADC results. Each result contains 2
bytes, with the MSB preceded by four leading zeros.
After each falling edge of CS, the oldest available byte of
data is available at DOUT, MSB first. When the FIFO is
empty, DOUT is zero.
The MAX11638/MAX11639/MAX11642/MAX11643 oper-
ate from an internal oscillator, which is accurate within
10% of the 4.4MHz nominal clock rate. The internal
Table 1. Input Data Byte (MSB First)
X = Don’t care.
Conversion
Setup
Averaging
Reset
REGISTER NAME
IN
t
ACQ
= 1.5kΩ, R
True Differential Analog Input T/H
ACQ
= 9 x (R
or by placing a 1µF capacitor between
PWR
______________________________________________________________________________________
S
S
= 1µs, the power-up time of the
is the source impedance of the
+ R
BIT 7
1
0
0
0
IN
) x 24pF + t
8-Bit, 16-/8-Channel, 300ksps ADCs
ACQ
ACQ
with FIFO and Internal Reference
CHSEL3
is never less than
Internal Clock
BIT 6
, is the maximum
Internal FIFO
1
0
0
PWR
CHSEL2
CKSEL1
BIT 5
1
0
CHSEL1
CKSEL0
AVGON
oscillator is active in clock modes 00, 01, and 10. Read
out the data at clock speeds up to 10MHz. See Figures
4–7 for details on timing specifications and starting a
conversion.
The MAX11638/MAX11639/MAX11642/MAX11643 com-
municate between the internal registers and the exter-
nal circuitry through the SPI-/QSPI-compatible serial
interface. Table 1 details the registers and the bit
names. Tables 2–5 show the various functions within
the conversion register, setup register, averaging regis-
ter, and reset register.
The conversion time for each scan is based on a num-
ber of different factors: conversion time per sample,
samples per result, results per scan, and if the external
reference is in use.
Use the following formula to calculate the total conver-
sion time for an internally timed conversion in clock
modes 00 and 10 (see the Electrical Characteristics
section as applicable):
where:
In clock mode 01, the total conversion time depends on
how long CNVST is held low or high, including any time
required to turn on the internal reference. Conversion
time in externally clocked mode (CKSEL1, CKSEL0 = 11)
depends on the SCLK period and how long CS is held
high between each set of eight SCLK cycles. In clock
mode 01, the total conversion time does not include the
time required to turn on the internal reference.
BIT 4
Total Conversion Time = t
1
t
n
n
determined by the number of channels being
scanned or by NSCAN1, NSCAN0
t
nal reference is already powered up or external ref-
erence is being used
CNV
RP
AVG
RESULT
= internal reference wake-up; set to zero if inter-
= t
= samples per result (amount of averaging)
REFSEL1
CHSEL0
NAVG1
RESET
ACQ
BIT 3
= number of FIFO results requested;
Applications Information
(max) + t
REFSEL0
NAVG0
SCAN1
Conversion Time Calculations
BIT 2
X
CONV
CNV
Register Descriptions
x n
(max)
NSCAN1
AVG
SCAN0
BIT 1
X
X
x n
RESULT
NSCAN0
BIT 0
X
X
X
+ t
RP
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