DS21448A1 Maxim Integrated, DS21448A1 Datasheet - Page 12

• Manufacturer Part Number: DS21448A1
• Description: Network Controller & Processor ICs 3.3V E1/T1/J1 Quad Interface
• Manufacturer: Maxim Integrated

Specifications of DS21448A1

• Part # Aliases: 90-21448-0A1

BPCLK1–BPCLK4
RRING1–RRING4
TRING1–TRING4
RNEG1–RNEG4
RPOS1–RPOS4
PBEO1–PBEO4
TNEG1–TNEG4
TPOS1–TPOS4
TVDD1–TVDD4
LOOP0/LOOP1
RCLK1–RCLK4
TCLK1–TCLK4
RTIP1–RTIP4
TTIP1–TTIP4
VDD1–VDD4
EGL1–EGL4
RCL1–RCL4
MM0/MM1
BIS0/BIS1
RT1/RT0
TX0/TX1
JTRST
JTCLK
MCLK
JTMS
JTDO
TEST
HRST
JTDI
VSM
CES
TPD
PIN
I/O
—
O
O
O
O
O
O
O
O
–
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Receive and Transmit Clock Select. Selects which RCLK edge to update RPOS and RNEG and
which TCLK edge to sample TPOS and TNEG. CES combines TCES and RCES.
0 = update RPOS/RNEG on rising edge of RCLK; sample TPOS/TNEG on falling edge of TCLK
1 = update RPOS/RNEG on falling edge of RCLK; sample TPOS/TNEG on rising edge of TCLK
Transmit Power-Down
0 = normal transmitter operation
1 = powers down the transmitter and tri-states TTIP and TRING pins
Transmit Data Source Select Bits 0 and 1. These inputs determine the source of the transmit
data
Loopback Select Bits 0 and 1. These inputs determine the active loopback mode
Monitor Mode Select Bits 0 and 1. These inputs determine if the receive equalizer is in a monitor
mode
Receive LIU Termination Select Bits 0 and 1. These inputs determine the receive termination
(Table
Tri-State Control. Set high to tri-state all outputs and I/O pins (including the parallel control port).
Set low for normal operation. Useful in board-level testing.
Hardware Reset. Bringing HRST low resets the DS21448, setting all control bits to the all-zero
default state.
Master Clock. A 2.048MHz (±50ppm) clock source with TTL levels is applied at this pin. This
clock is used internally for both clock/data recovery and for jitter attenuation. A T1 1.544MHz
clock source is optional (Note 1). See
Bus Interface Select Bit 0 and 1. Used to select bus interface option
Receive Equalizer Gain-Limit Select. These bits control the sensitivity of the receive equalizers
(Table
PRBS Bit-Error Output. The receiver constantly searches for a 2
QRSS PRBS (ETS = 1). The pattern is chosen automatically by the value of the ETS pin. It
remains high if it is out of synchronization with the PRBS pattern. It goes low when synchronized
to the PRBS pattern. Any errors in the received pattern after synchronization cause a positive-
going pulse (with same period as E1 or T1 clock) synchronous with RCLK.
Receive Carrier Loss. An output that toggles high during a receive carrier loss.
Receive Tip and Ring. Analog inputs for clock recovery circuitry. These pins connect through a
1:1 transformer to the line. See Section
Backplane Clock. A 16.384MHz clock output that is referenced to RCLK.
Transmit Tip and Ring. Analog line-driver outputs. These pins connect through a step-up
transformer to the line. See Section
Receive Positive Data. Updated on the rising edge (CES = 0) or the falling edge (CES = 1) of
RCLK with bipolar data out of the line interface. In NRZ mode (NRZE = 1), data is output on
RPOS, and a received error (BPV, CV, or EXZ) causes a positive-going pulse synchronous with
RCLK at RNEG.
Receive Negative Data. Updated on the rising edge (CES = 0) or the falling edge (CES = 1) of
RCLK with bipolar data out of the line interface. In NRZ mode (NRZE = 1), data is output on
RPOS, and a received error (BPV, CV, or EXZ) causes a positive-going pulse synchronous with
RCLK at RNEG.
Receive Clock. Buffered recovered clock from the line. Synchronous to MCLK in absence of
signal at RTIP and RRING.
Transmit Positive Data. Sampled on the falling edge (CES = 0) or the rising edge (CES = 1) of
TCLK for data to be transmitted out onto the line.
Transmit Negative Data. Sampled on the falling edge (CES = 0) or the rising edge (CES = 1) of
TCLK for data to be transmitted out onto the line.
Transmit Clock. A 2.048MHz or 1.544MHz primary clock used to clock data through the transmit
side formatter. It can be sourced internally by MCLK or RCLK. See Common Control Register 1
and
JTAG Reset
JTAG Mode Select
JTAG Clock
JTAG Data In
JTAG Data Out
Voltage Supply Mode (LQFP only). VSM should be wired low for correct operation.
3.3V, ±5% Transmitter Positive Supply
3.3V, ±5% Positive Supply
Figure
(Table
(Table
4-E).
4-C).
1-3.
4-B).
4-D).
12 of 60
7
for details.
Table 4-F
7
for details.
FUNCTION
for details.
15
- 1 PRBS (ETS = 0) or a
(Table
2-A).
(Table
4-A).