DS21448A1 Maxim Integrated, DS21448A1 Datasheet - Page 34

• Manufacturer Part Number: DS21448A1
• Description: Network Controller & Processor ICs 3.3V E1/T1/J1 Quad Interface
• Manufacturer: Maxim Integrated

Specifications of DS21448A1

• Part # Aliases: 90-21448-0A1

10Hz to 100kHz) is added to the jitter present on TCLK. Also, the waveforms created are independent of the duty
cycle of TCLK. The transmitter couples to the E1 or T1 transmit-twisted pair (or coaxial cable in some E1
applications) through a 1:2 step-up transformer. For the device to create the proper waveforms, the transformer
used must meet the specifications listed in
The DS21448 has an automatic short-circuit limiter that limits the source current to 50mA (RMS) into a 1Ω load.
This feature can be disabled by setting the SCLD bit (CCR2.5) = 1. When the current limiter is activated, TCLE
(SR.2) is set even if the short-circuit limiter is disabled. The TPD bit (CCR4.0) powers down the transmit-line driver
and tri-states the TTIP and TRING pins. The DS21448 can also detect when the TTIP or TRING outputs are open
circuited. When an open circuit is detected, TOCD (SR.1) is set.
7.3 Jitter Attenuator
The DS21448 contains an on-board jitter attenuator that can be set to a depth of either 32 or 128 bits through the
JABDS bit (CCR4.2). The 128-bit mode is used in applications where large excursions of wander are expected.
The 32-bit mode is used in delay-sensitive applications.
attenuator can be placed in either the receive path or the transmit path by appropriately setting or clearing the JAS
bit (CCR4.3). Also, setting the DJA bit (CCR4.1) can disable the jitter attenuator (in effect, remove it). For the jitter
attenuator to operate properly, a 2.048MHz or 1.544MHz clock must be applied at MCLK. ITU specification G.703
requires ±50ppm accuracy for T1 and E1. TR62411 and ANSI specs require ±32ppm accuracy for T1 interfaces.
An on-board PLL for the jitter attenuator converts the 2.048MHz clock to a 1.544MHz rate for T1 applications.
Setting JAMUX (CCR1.3) to logic 0 bypasses this PLL. On-board circuitry adjusts either the recovered clock from
the clock/data recovery block or the clock applied at the TCLK pin to create a smooth jitter-free clock, which is used
to clock data out of the jitter attenuator FIFO. It is acceptable to provide a gapped/bursty clock at the TCLK pin if
the jitter attenuator is placed on the transmit side. If the incoming jitter exceeds either 120UI
bits) or 28UI
(T1) clock by either 15 or 17 instead of the normal 16 to keep the buffer from overflowing. When the device divides
by either 15 or 17, it also sets the JALT bit in the receive information register 1 (RIR1).
7.4 G.703 Synchronization Signal
The DS21448 can receive a 2.048MHz square-wave synchronization clock, as specified in Section 10 of ITU
G.703. To use the DS21448 in this mode, set the receive-synchronization-clock enable (CCR5.3) = 1. The
DS21448 can also transmit the 2.048MHz square-wave synchronization clock, as specified in Section 10 of G.703.
To transmit the 2.048MHz clock, set the transmit-synchronization-clock enable (CCR5.2) = 1.
Table 7-A. Line Build-Out Select for E1 in Register CCR4 (ETS = 0)
Table 7-B. Line Build-Out Select for T1 in Register CCR4 (ETS = 1)
Note: See
N.M. = Not meaningful.
L2
L2
0
0
1
1
0
0
0
0
1
1
1
1
L1
L1
0
0
0
0
0
0
1
1
0
0
1
1
Figure
P-P
L0
L0
7-1,
0
1
0
1
0
1
0
1
0
1
0
1
(buffer depth is 32 bits), the DS21448 divides the internal nominal 32.768MHz (E1) or 24.704MHz
Figure
DSX-1 (0 to 133ft)/0dB CSU
7-2, and
120Ω with high return loss
75Ω with high return loss
DSX-1 (266 to 399ft)
DSX-1 (399 to 533ft)
DSX-1 (533 to 655ft)
DSX-1 (133 to 266f)
APPLICATION
APPLICATION
-22.5dB CSU
120Ω normal
-7.5dB CSU
75Ω normal
-15dB CSU
Figure
7-3.
Table
7-C.
34 of 60
1:2
1:2
1:2
1:2
1:2
1:2
1:2
1:2
1:2
1:2
1:2
1:2
N
N
Figure 7-8
RETURN LOSS
RETURN LOSS
21dB
21dB
shows the attenuation characteristics. The jitter
N.M.
N.M.
N.M.
N.M.
N.M.
N.M.
N.M.
N.M.
N.M.
N.M.
R
R
11.6
6.2
t
t
0
0
0
0
0
0
0
0
0
0
(Ω)
(Ω)
P-P
(buffer depth is 128