CY7C1512JV18-267BZI Cypress Semiconductor Corp, CY7C1512JV18-267BZI Datasheet
CY7C1512JV18-267BZI
Specifications of CY7C1512JV18-267BZI
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CY7C1512JV18-267BZI Summary of contents
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... To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with two 9-bit words (CY7C1525JV18), 18-bit words (CY7C1512JV18), or 36-bit words (CY7C1514JV18) that burst sequentially into or out of the device. Because data is transferred into and out of the ...
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... Logic Block Diagram (CY7C1525JV18 [8:0] 21 Address A (20:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [0] Logic Block Diagram (CY7C1512JV18 [17:0] 21 Address A (20:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [1:0] Document #: 001-14435 Rev. *G Write Write Address Reg Reg ...
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... Logic Block Diagram (CY7C1514JV18 [35:0] 20 Address A (19:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [3:0] Document #: 001-14435 Rev. *G Write Write Address Reg Reg Register Control Logic Read Data Reg Reg. Reg. 36 Reg. CY7C1525JV18 CY7C1512JV18 CY7C1514JV18 20 A (19:0) RPS [35:0] Page [+] Feedback ...
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... Pin Configuration The pin configuration for CY7C1525JV18, CY7C1512JV18, and CY7C1514JV18 follow DOFF V V REF DDQ TDO TCK NC/144M D10 D NC D11 Q10 Q11 F NC Q12 D12 G NC D13 Q13 H DOFF V V REF DDQ D14 Q14 L NC Q15 D15 D16 N NC D17 ...
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... Pin Configuration The pin configuration for CY7C1525JV18, CY7C1512JV18, and CY7C1514JV18 follow NC/288M A B Q27 Q18 D18 C D27 Q28 D19 D D28 D20 Q19 E Q29 D29 Q20 F Q30 Q21 D21 G D30 D22 Q22 H DOFF V V REF DDQ J D31 Q31 D23 K Q32 D32 Q23 ...
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... These address inputs are multiplexed for both read and write operations. Internally, the device is organized arrays each for CY7C1525JV18 arrays each 18) for CY7C1512JV18, and arrays each 36) for CY7C1514JV18. Therefore, only 22 address inputs are needed to access the entire memory array of CY7C1525JV18, 21 address inputs for CY7C1512JV18, and 20 address inputs for CY7C1514JV18 ...
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... Ground Ground for the Device Power Supply Power Supply Inputs for the Outputs of the Device. DDQ Document #: 001-14435 Rev. *G Pin Description output impedance are set to 0.2 x RQ, where resistor connected [x:0] DDQ CY7C1525JV18 CY7C1512JV18 CY7C1514JV18 , which enables the minimum Page [+] Feedback ...
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... This includes forwarding data from a write cycle that was initiated on the previous K clock rise. Depth Expansion The CY7C1512JV18 has a port select input for each port. This enables easy depth expansion. Both port selects are sampled on using the rising edge of the positive input clock only (K). Each port [17:0] select input can deselect the specified port ...
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... DOFF pin. When the DLL is turned off, the device behaves in QDR I mode (with one cycle latency and a longer access time). For information refer to the application note DLL Considerations in QDRII/DDRII. Figure 1. Application Example SRAM # 250ohms CQ/CQ Vddq/2 CY7C1525JV18 CY7C1512JV18 CY7C1514JV18 SRAM # 250ohms CQ/CQ ...
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... Truth Table The truth table for CY7C1525JV18, CY7C1512JV18, and CY7C1514JV18 follows. Operation Write Cycle: Load address on the rising edge of K; input write data on K and K rising edges. Read Cycle: Load address on the rising edge of K; wait one and a half cycle; read data on C and C rising edges. ...
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... No data is written into the device during this portion of a write operation. L–H No data is written into the device during this portion of a write operation. CY7C1525JV18 CY7C1512JV18 CY7C1514JV18 ) is written into the device. [8: written into the device. [8:0] ) are written into ...
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... TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction after it is shifted in, move the TAP controller into the Update-IR state. CY7C1525JV18 CY7C1512JV18 CY7C1514JV18 TAP Controller Block Diagram on on page 18 shows the order in which ...
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... Q-bus pins. Note that this bit is pre-set LOW to enable the output when the device is powered up, and also when the TAP controller is in the Test-Logic-Reset state. CS Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. CY7C1525JV18 CY7C1512JV18 CY7C1514JV18 Page [+] Feedback ...
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... Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 001-14435 Rev. *G [9] 1 SELECT DR-SCAN 0 1 CAPTURE- SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- CY7C1525JV18 CY7C1512JV18 CY7C1514JV18 1 SELECT IR-SCAN 0 1 CAPTURE- SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- Page [+] Feedback ...
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... Boundary Scan Register TAP Controller Test Conditions = −2 −100 μ 2 100 μ GND ≤ V ≤ − /2), Undershoot: V (AC) > 1.5V (Pulse width less than t CYC IL CY7C1525JV18 CY7C1512JV18 CY7C1514JV18 Selection TDO Circuitry Min Max Unit 1.4 V 1.6 V 0.4 V 0.2 V 0.65V –0.3 0.35V V DD μ ...
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... Test conditions are specified using the load in TAP AC Test Conditions. t Document #: 001-14435 Rev. *G Description [14] Figure 2. TAP Timing and Test Conditions 0.9V 1.8V 50Ω TMSH t TMSS t TDIS t TDIH t TDOV / ns CY7C1525JV18 CY7C1512JV18 CY7C1514JV18 Min Max Unit 50 20 MHz ALL INPUT PULSES 0.9V t TCYC t TDOX Page ...
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... Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. CY7C1525JV18 CY7C1512JV18 CY7C1514JV18 Description 000 Version number. Defines the type of SRAM ...
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... Bit # Bump ID 10G 11F 58 5A 11G 10F 61 4B 11E 62 3A 10E 63 2A 10D 10C 66 3B 11D 11B 70 3C 11C 10B 73 3E 11A 74 2D 10A CY7C1525JV18 CY7C1512JV18 CY7C1514JV18 Bit # Bump 100 2P 101 1P 102 3R 103 4R 104 4P 105 5P 106 5N 107 5R 108 Internal Page [+] Feedback ...
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... SRAM behavior. To avoid this, provide1024 cycles stable clock to relock to the desired clock frequency. . REF Figure 3. Power Up Waveforms > 1024 Stable clock Stable DDQ Stable (< +/- 0.1V DC per 50ns ) / DDQ Fix High (or tie to V DDQ ) CY7C1525JV18 CY7C1512JV18 CY7C1514JV18 . KC Var Start Normal Operation Page [+] Feedback ...
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... MHz (min) within 200 ms. During this time V < V and /2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms. (max) = 0.95V or 0.54V , whichever is smaller. REF DDQ CY7C1525JV18 CY7C1512JV18 CY7C1514JV18 Test Description Typ Max* Unit Conditions Logical 25°C 320 368 Single-Bit Upsets Logical 25° ...
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... R = 50Ω REF OUTPUT DEVICE 0.25V 5 pF UNDER ZQ TEST RQ = 250Ω INCLUDING JIG AND (b) SCOPE /I and load capacitance shown in ( CY7C1525JV18 CY7C1512JV18 CY7C1514JV18 Min Typ Max 400 420 455 365 385 420 Min Typ Max V + 0.2 – – REF – – ...
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... An input jitter of 200 ps (t KHKH Waveforms. Transition is measured ± 100 mV from steady state voltage. AC Test Loads and and t less than t . CLZ CHZ CO CY7C1525JV18 CY7C1512JV18 CY7C1514JV18 267 MHz 250 MHz Unit Min Max Min Max 3.75 8.4 4 ...
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... Document #: 001-14435 Rev. *G WRITE WRITE READ NOP KHKH t CYC D31 D50 D51 D60 Q00 Q01 Q20 t CLZ t CQDOH t DOH CYC t CCQO t CQOH t CCQO CY7C1525JV18 CY7C1512JV18 CY7C1514JV18 [26, 27, 28] WRITE NOP D61 Q21 Q40 Q41 t CHZ t CQD t CQHCQH t CQH DON’T CARE UNDEFINED Page [+] Feedback ...
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... Fine Pitch Ball Grid Array ( 1.4 mm) 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) Pb-Free 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm 0.15(4X) CY7C1525JV18 CY7C1512JV18 CY7C1514JV18 and refer to the product summary page at Operating Range Commercial Industrial BOTTOM VIEW PIN 1 CORNER Ø ...
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... Document History Page Document Title: CY7C1525JV18/CY7C1512JV18/CY7C1514JV18, 72-Mbit QDR Document Number: 001-14435 Orig. Of Submission Rev. ECN No. Change ** 1060980 VKN *A 1397384 VKN *B 1462588 VKN/AESA *C 2189567 VKN/AESA *D 2561954 VKN/PYRS *E 2612311 VKN/PYRS *F 2746930 NJY 07/31/2009 *G 2751694 VKN/AESA 08/13/2009 Document #: 001-14435 Rev. *G Description Of Change Date See ECN ...
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... QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders. psoc.cypress.com clocks.cypress.com image.cypress.com Revised August 10, 2009 CY7C1525JV18 CY7C1512JV18 CY7C1514JV18 Page [+] Feedback ...