CY7C1512JV18-267BZI Cypress Semiconductor Corp, CY7C1512JV18-267BZI Datasheet - Page 9

• Manufacturer Part Number: CY7C1512JV18-267BZI
• Description: IC SRAM 72MBIT 267MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1512JV18-267BZI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 72M (4M x 18)
• Speed: 267MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Echo Clocks
Echo clocks are provided on the QDR II to simplify data capture
on high speed systems. Two echo clocks are generated by the
QDR II. CQ is referenced with respect to C and CQ is referenced
with respect to C. These are free running clocks and are synchro-
nized to the output clock of the QDR II. In the single clock mode,
CQ is generated with respect to K and CQ is generated with
respect to K. The timing for the echo clocks is shown in
Characteristics
Application Example
Figure 1
Document #: 001-14435 Rev. *G
MASTER
ASIC)
(CPU
BUS
or
shows two QDR II used in an application.
CLKIN/CLKIN#
Delayed K#
DATA OUT
Delayed K
Source K#
on page 22.
Source K
Address
DATA IN
BWS#
WPS#
RPS#
Vt
R
R
R = 50ohms
D
A
R
P
S
#
Vt = Vddq/2
W
P
S
#
SRAM #1
Figure 1. Application Example
W
B
S
#
Switching
C C#
CQ/CQ#
K
ZQ
K#
Q
R = 250ohms
DLL
These chips use a DLL that is designed to function between
120 MHz and the specified maximum clock frequency. During
power up, when the DOFF is tied HIGH, the DLL is locked after
1024 cycles of stable clock. The DLL is also reset by slowing or
stopping the input clocks K and K for a minimum of 30 ns.
However, it is not necessary to reset the DLL to lock to the
desired frequency. The DLL automatically locks 1024 clock
cycles after a stable clock is presented. Disable the DLL by
applying ground to the DOFF pin. When the DLL is turned off,
the device behaves in QDR I mode (with one cycle latency and
a longer access time). For information refer to the application
note DLL Considerations in QDRII/DDRII.
D
A
R
Vt
Vt
R
P
S
#
W
P
S
#
W
B
S
#
SRAM #2
CY7C1525JV18
CY7C1512JV18
CY7C1514JV18
C C#
CQ/CQ#
K
ZQ
K#
Q
R = 250ohms
Page 9 of 26
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