M45PE80-VMP6TG NUMONYX, M45PE80-VMP6TG Datasheet - Page 24

• Manufacturer Part Number: M45PE80-VMP6TG
• Description: IC FLASH 8MBIT 50MHZ 8VFQFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M45PE80-VMP6TG

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 50MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VFQFN, 8-VFQFPN
• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 12ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VFQFPN
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 4mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M45PE80-VMP6TG; M45PE80-VMP6TGTR

24/48
If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be written correctly within the same page. If less than
256 Data bytes are sent to device, they are correctly written at the requested addresses
without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the Page Write (PW) instruction to write all
consecutive targeted bytes in a single sequence versus using several Page Write (PW)
sequences with each containing only a few bytes (see
operation)
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Page Write (PW) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Write cycle (whose duration
is t
read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is
1 during the self-timed Page Write cycle, and is 0 when it is completed. At some unspecified
time before the cycle is complete, the Write Enable Latch (WEL) bit is reset.
A Page Write (PW) instruction applied to a page that is Hardware Protected is not executed.
Any Page Write (PW) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
Figure 12. Page Write (PW) instruction sequence
1. Address bits A23 to A20 are Don’t Care
2. 1 ≤ n ≤ 256
PW
S
C
D
S
C
D
) is initiated. While the Page Write cycle is in progress, the Status Register may be
MSB
and
7
40
0
6
41
Table 14.: AC characteristics (75 MHz
1
5
42
Data Byte 2
2
Instruction
4
43 44 45 46 47 48 49 50
3
3
4
2
5
1
6
0
MSB
7
7
MSB
23
8
6
22 21
9 10
5
Data Byte 3
24-Bit Address
4
51
3
52 53 54 55
3
28 29 30 31 32 33 34 35
2
2
1
1
operation)).
Table 13: AC characteristics (50 MHz
0
0
MSB
7
MSB
7
6
6
5
Data Byte 1
5
Data Byte n
4
4
3
36 37 38
3
2
2
1
1
0
39
0
AI04045