M45PE80-VMP6TG NUMONYX, M45PE80-VMP6TG Datasheet - Page 30

• Manufacturer Part Number: M45PE80-VMP6TG
• Description: IC FLASH 8MBIT 50MHZ 8VFQFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M45PE80-VMP6TG

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 50MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VFQFN, 8-VFQFPN
• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 12ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VFQFPN
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 4mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M45PE80-VMP6TG; M45PE80-VMP6TGTR

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Release from Deep Power-down (RDP)
To exit from Deep Power-down mode, the Release from Deep Power-down (RDP)
instruction must be issued. No other instruction must be issued while the device is in this
mode.
The Release from Deep Power-down (RDP) instruction is entered by driving Chip Select (S)
Low, followed by the instruction code on Serial Data Input (D). Chip Select (S) must be
driven Low for the entire duration of the sequence.
The instruction sequence is shown in
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select
(S) High. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is driven
Low, cause the instruction to be rejected, and not executed.
After Chip Select (S) has been driven High, followed by a delay, t
Standby mode. Chip Select (S) must remain High at least until this period is over. The
device waits to be selected, so that it can receive, decode and execute instructions.
Any Release from Deep Power-down (RDP) instruction, while an Erase, Program or Write
cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 17. Release from Deep Power-down (RDP) instruction sequence
S
C
D
Q
High Impedance
0
1
2
Instruction
3
4
5
6
Figure
7
17.
Deep Power-down Mode
t
RDP
RDP
, the device is put in the
Stand-by Mode
AI06807