M45PE80-VMP6TG NUMONYX, M45PE80-VMP6TG Datasheet - Page 8

• Manufacturer Part Number: M45PE80-VMP6TG
• Description: IC FLASH 8MBIT 50MHZ 8VFQFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M45PE80-VMP6TG

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 50MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VFQFN, 8-VFQFPN
• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 12ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VFQFPN
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 4mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M45PE80-VMP6TG; M45PE80-VMP6TGTR

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Signal description
Serial Data Output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
Serial Data Input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are latched on the rising edge of Serial
Clock (C).
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
Chip Select (S)
When this input signal is High, the device is deselected and Serial Data Output (Q) is at high
impedance. Unless an internal Read, Program, Erase or Write cycle is in progress, the
device will be in the Standby mode (this is not the Deep Power-down mode). Driving Chip
Select (S) Low enables the device, placing it in the active power mode.
After Power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
Reset (Reset)
The Reset (Reset) input provides a hardware reset for the memory.
When Reset (Reset) is driven High, the memory is in the normal operating mode.
When Reset (Reset) is driven Low, the device enters the Reset mode. In this mode, the
output Q is high impedance:
If an internal operation (Write, Erase or Program cycle) is in progress when Reset (Reset) is
driven Low, the device enters the Reset mode and any on-going Write, Program or Erase
cycle is aborted. The addressed data may be lost.
Write Protect (W)
This input signal puts the device in the Hardware Protected mode, when Write Protect (W) is
connected to V
them from write, program and erase operations. When Write Protect (W) is connected to
V
CC
, the first 256 pages of memory behave like the other pages of memory.
SS
, causing the first 256 pages of memory to become read-only by protecting