STK12C68-SF45I Cypress Semiconductor Corp, STK12C68-SF45I Datasheet - Page 4

• Manufacturer Part Number: STK12C68-SF45I
• Description: IC NVSRAM 64KBIT 45NS 28SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: -r

Specifications of STK12C68-SF45I

• Memory Size: 64K (8K x 8)
• Package / Case: 28-SOIC (8.69mm width)
• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 45 ns
• Supply Voltage (max): 7 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 65 mA
• Organization: 8 K x 8
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 4.5 V to 5.5 V
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

Device Operation
The STK12C68 nvSRAM is made up of two functional compo-
nents paired in the same physical cell. These are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM Read and Write operations are inhibited. The
STK12C68 supports unlimited reads and writes similar to a
typical SRAM. In addition, it provides unlimited RECALL opera-
tions from the nonvolatile cells and up to one million STORE
operations.
SRAM Read
The STK12C68 performs a Read cycle whenever CE and OE are
LOW while WE and HSB are HIGH. The address specified on
pins A
Read is initiated by an address transition, the outputs are valid
after a delay of t
or OE, the outputs are valid at t
(Read cycle 2). The data outputs repeatedly respond to address
changes within the t
tions on any control input pins, and remains valid until another
address change or until CE or OE is brought HIGH, or WE or
HSB is brought LOW.
SRAM Write
A Write cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs must be stable prior to entering
the Write cycle and must remain stable until either CE or WE
goes HIGH at the end of the cycle. The data on the common I/O
pins DQ
the end of a WE controlled Write or before the end of an CE
controlled Write. Keep OE HIGH during the entire Write cycle to
avoid data bus contention on common I/O lines. If OE is left LOW,
internal circuitry turns off the output buffers t
LOW.
AutoStore Operation
The STK12C68 stores data to nvSRAM using one of three
storage operations:
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the STK12C68.
Document Number: 001-51027 Rev. *D
1. Hardware store activated by HSB
2. Software store activated by an address sequence
3. AutoStore on device power down
0–12
0–7
determines the 8,192 data bytes accessed. When the
are written into the memory if it has valid t
AA
(Read cycle 1). If the Read is initiated by CE
AA
access time without the need for transi-
ACE
or at t
DOE
HZWE
, whichever is later
after WE goes
SD
, before
During normal operation, the device draws current from V
charge a capacitor connected to the V
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
automatically disconnects the V
operation is initiated with power provided by the V
Figure 2
(V
between 68 µF and 220 µF (+20%) rated at 6V should be
provided. The voltage on the V
pump internal to the chip. A pull up is placed on WE to hold it
inactive during power up.
Figure 2. AutoStore Mode
In system power mode, both V
+5V power supply without the 68 μF capacitor. In this mode, the
AutoStore function of the STK12C68 operates on the stored
system charge as power goes down. The user must, however,
guarantee that V
STORE cycle.
To reduce unnecessary nonvolatile stores, AutoStore, and
Hardware Store operations are ignored, unless at least one Write
operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a Write operation has taken place. An
optional pull up resistor is shown connected to
signal is monitored by the system to detect if an AutoStore cycle
is in progress.
CAP
) for automatic store operation. A charge storage capacitor
shows the proper connection of the storage capacitor
CC
does not drop below 3.6V during the 10 ms
CC
pin drops below V
CAP
CC
CAP
and V
pin is driven to 5V by a charge
pin from V
CAP
CAP
are connected to the
STK12C68
pin. This stored
SWITCH
HSB.
CC
CAP
Page 4 of 23
. A STORE
, the part
capacitor.
The HSB
CC
to
[+] Feedback