STK12C68-SF45I Cypress Semiconductor Corp, STK12C68-SF45I Datasheet - Page 5

• Manufacturer Part Number: STK12C68-SF45I
• Description: IC NVSRAM 64KBIT 45NS 28SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: -r

Specifications of STK12C68-SF45I

• Memory Size: 64K (8K x 8)
• Package / Case: 28-SOIC (8.69mm width)
• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 45 ns
• Supply Voltage (max): 7 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 65 mA
• Organization: 8 K x 8
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 4.5 V to 5.5 V
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

Figure 3. AutoStore Inhibit Mode
If the power supply drops faster than 20 us/volt before Vcc
reaches V
between V
of current between V
AutoStore Inhibit Mode
If an automatic STORE on power loss is not required, then V
is tied to ground and +5V is applied to V
the AutoStore Inhibit mode, where the AutoStore function is
disabled. If the STK12C68 is operated in this configuration, refer-
ences to V
In this mode, STORE operations are triggered through software
control or the HSB pin. To enable or disable Autostore using an
I/O port pin see
to change between these three options “on the fly”.
Hardware STORE (HSB) Operation
The STK12C68 provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin is used to
request a hardware STORE cycle. When the HSB pin is driven
LOW, the STK12C68 conditionally initiates a STORE operation
after t
SRAM takes place since the last STORE or RECALL cycle. The
HSB pin also acts as an open drain driver that is internally driven
LOW to indicate a busy condition, while the STORE (initiated by
any means) is in progress.
SRAM Read and Write operations, that are in progress when
HSB is driven LOW by any means, are given time to complete
before the STORE operation is initiated. After HSB goes LOW,
Document Number: 001-51027 Rev. *D
DELAY
SWITCH
CC
CC
. An actual STORE cycle only begins if a Write to the
and the system supply to avoid momentary excess
are changed to V
Preventing Store
, then a 2.2 ohm resistor should be connected
CC
and V
CAP
CAP
on page
.
throughout this data sheet.
CAP
6.
It is not permissible
(Figure
3). This is
CC
the STK12C68 continues SRAM operations for t
t
in progress when HSB is pulled LOW, it allows a time, t
complete. However, any SRAM Write cycles requested after
HSB goes LOW are inhibited until HSB returns HIGH.
During any STORE operation, regardless of how it is initiated,
the STK12C68 continues to drive the HSB pin LOW, releasing it
only when the STORE is complete. After completing the STORE
operation, the STK12C68 remains disabled until the HSB pin
returns HIGH.
If HSB is not used, it is left unconnected.
Hardware RECALL (Power Up)
During power up or after any low power condition (V
V
once again exceeds the sense voltage of V
cycle is automatically initiated and takes t
If the STK12C68 is in a Write state at the end of power up
RECALL, the SRAM data is corrupted. To help avoid this
situation, a 10 Kohm resistor is connected either between WE
and system V
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The STK12C68 software STORE
cycle is initiated by executing sequential CE controlled Read
cycles from six specific address locations in exact order. During
the STORE cycle, an erase of the previous nonvolatile data is
first performed followed by a program of the nonvolatile
elements. When a STORE cycle is initiated, input and output are
disabled until the cycle is completed.
Because a sequence of Reads from specific addresses is used
for STORE initiation, it is important that no other Read or Write
accesses intervene in the sequence. If they intervene, the
sequence is aborted and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following Read
sequence is performed:
The software sequence is clocked with CE controlled Reads or
OE controlled Reads. When the sixth address in the sequence
is entered, the STORE cycle commences and the chip is
disabled. It is important that Read cycles and not Write cycles
are used in the sequence. It is not necessary that OE is LOW for
a valid sequence. After the t
SRAM is again activated for Read and Write operation.
1. Read address 0x0000, Valid READ
2. Read address 0x1555, Valid READ
3. Read address 0x0AAA, Valid READ
4. Read address 0x1FFF, Valid READ
5. Read address 0x10F0, Valid READ
6. Read address 0x0F0F, Initiate STORE cycle
DELAY
RESET
, multiple SRAM Read operations take place. If a Write is
), an internal RECALL request is latched. When V
CC
or between CE and system V
STORE
cycle time is fulfilled, the
HRECALL
SWITCH
STK12C68
CC
.
DELAY
to complete.
Page 5 of 23
, a RECALL
DELAY
. During
CC
CC
to
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