MT48H4M16LFB4-8 IT Micron Technology Inc, MT48H4M16LFB4-8 IT Datasheet - Page 12

• Manufacturer Part Number: MT48H4M16LFB4-8 IT
• Description: IC SDRAM 64MBIT 125MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H4M16LFB4-8 IT

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Commands
Operation
commands. This is followed by a written description of
Table 6:
NOTE:
10. The purpose of the BURST TERMINATE command is to stop a data burst, thus the command could coincide with data on
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
NAME (FUNCTION)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE or DEEP POWER DOWN
(Enter deep power down mode)
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER/LOAD EXTENDED MODE
REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
1. CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER DOWN
2. A0-A11 define op-code written to mode register.
3. A0–A11 provide row address, and BA0, BA1 determine which bank is made active.
4. A0–A7 provide column address; A10 HIGH enables the auto precharge feature (non persistent), while A10 LOW disables
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). DQML controls DQ0-7,
9. This command is BURST TERMINATE when CKE is high and DEEP POWER DOWN when CKE is low.
Figure 6, Truth Table 1 – Commands and DQM
the auto precharge feature; BA0, BA1 determine which bank is being read from or written to.
Care.”
DQMH controls DQ8-15.
the bus. However the DQs column reads a don’t care state to illustrate that the BURST TERMINATE command can occur
when there is no data present.
1
provides a quick reference of available
Truth Table 1 – Commands and DQM Operation
CS# RAS# CAS# WE#
H
X
X
L
L
L
L
L
L
L
L
12
each command. Three additional Truth Tables appear
following the Operation section; these tables provide
current state/next state information.
X
H
H
H
H
X
X
L
L
L
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X
H
H
H
H
X
X
L
L
L
L
H
H
H
H
X
X
X
L
L
L
L
1
DQM
L/H
L/H
X
X
X
X
X
X
X
H
L
MOBILE SDRAM
Bank, A10
Bank/Row
Bank/Col
Bank/Col
Op-Code
©2003 Micron Technology, Inc. All rights reserved.
ADDR
X
X
X
X
X
X
64Mb: x16
High-Z
Active
Valid
DQS
X
X
X
X
X
X
X
X
NOTES
9, 10
6, 7
3
4
4
5
2
8
8