CY7C135-25JXC Cypress Semiconductor Corp, CY7C135-25JXC Datasheet - Page 9

• Manufacturer Part Number: CY7C135-25JXC
• Description: IC SRAM 32KBIT 25NS 52PLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C135-25JXC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 32K (4K x 8)
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 52-PLCC
• Density: 32Kb
• Access Time (max): 25ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 12b
• Package Type: PLCC
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 180mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 52
• Word Size: 8b
• Number Of Words: 4K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Architecture
The CY7C135/135A consists of an array of 4K words of 8 bits
each of dual-port RAM cells, I/O and address lines, and control
signals (CE, OE, R/W). Two semaphore control pins exist for the
CY7C1342 (SEM
Functional Description
Write Operation
Data must be set up for a duration of t
of R/W to guarantee a valid write. Because there is no on-chip
arbitration, the user must be sure that a specific location is not
accessed simultaneously by both ports or erroneous data could
result. A write operation is controlled by either the OE pin (see
Figure
t
of R/W. Required inputs for write operations are summarized in
Table
If a location is being written to by one port and the opposite port
attempts to read the same location, a port-to-port flowthrough
delay is met before the data is valid on the output. Data is valid
on the port wishing to read the location t
presented on the writing port.
Read Operation
When reading the device, the user must assert both the OE and
CE pins. Data is available t
asserted. If the user of the CY7C1342 wishes to access a
semaphore, the SEM pin must be asserted instead of the CE pin.
Required inputs for read operations are summarized in
Semaphore Operation
The CY7C1342 provides eight semaphore latches, which are
separate from the dual port memory locations. Semaphores are
used to reserve resources which are shared between the two
ports. The state of the semaphore indicates that a resource is in
use. For example, if the left port wants to request a given
resource, it sets a latch by writing a zero to a semaphore location.
The left port then verifies its success in setting the latch by
reading it. After writing to the semaphore, SEM or OE must be
deasserted for t
The semaphore value is available t
edge of the semaphore write. If the left port was successful
(reads a zero), it assumes control over the shared resource,
otherwise (reads a one) it assumes the right port has control and
continues to poll the semaphore. When the right side has relin-
quished control of the semaphore (by writing a one), the left side
succeeds in gaining control of the semaphore. If the left side no
longer requires the semaphore, a one is written to cancel its
request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip enable for the semaphore latches. CE
must remain HIGH during SEM LOW. A
semaphore address. OE and R/W are used in the same manner
as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O
to the left port of an unused semaphore, a one appears at the
same semaphore address on the right port. That semaphore can
Document #: 38-06038 Rev. *D
HZOE
1.
after the OE is deasserted or t
7) or the R/W pin (see
SOP
L/R
).
before attempting to read the semaphore.
ACE
Figure
after CE or t
SWRD
HZWE
SD
8). Data can be written
0
is used. If a 0 is written
before the rising edge
+ t
DDD
after the falling edge
0–2
DOE
DOE
after the data is
represents the
after the rising
after OE are
Table
1.
now only be modified by the side showing a zero (the left port in
this case). If the left port now relinquishes control by writing a one
to the semaphore, the semaphore is set to one for both sides.
However, if the right port had requested the semaphore (written
a zero) while the left port had control, the right port would immedi-
ately own the semaphore.
operations.
When reading a semaphore, all eight data lines output the
semaphore value. The read value is latched in an output register
to prevent the semaphore from changing state during a write
from the other port. If both ports request a semaphore control by
writing a 0 to a semaphore within t
guaranteed that only one side gains access to the semaphore.
Initialization of the semaphore is not automatic and must be reset
during initialization program during power up. All semaphores on
both sides should have a one written into them at initialization
from both sides to assure that they are free when needed.
Table 1. Non-Contending Read/Write
Table 2. Semaphore Operation Example
No action
Left port writes
semaphore
Right port writes 0 to
semaphore
Left port writes 1 to
semaphore
Left port writes 0 to
semaphore
Right port writes 1 to
semaphore
Left port writes 1 to
semaphore
Right port writes 0 to
semaphore
Right port writes 1 to
semaphore
Left port writes 0 to
semaphore
Left port writes 1 to
semaphore
CE R/W OE
H
H
X
H
L
L
L
Function
X
H
X
H
X
L
L
Inputs
X
H
X
X
X
L
L
SEM
H
X
H
H
L
L
L
I/O
Left
High Z
Data Out
High Z
Data In
Data Out
Data In
1
0
0
1
1
0
1
1
1
0
1
0-7
I/O
CY7C135, CY7C135A
Outputs
Table 2
0
Right
– I/O
I/O
1
1
1
0
0
1
1
0
1
1
1
0-7
7
shows sample semaphore
SPS
Semaphore free
Left port obtains
semaphore
Right side is denied
access
Right port is granted
access to Semaphore
No change. Left port is
denied access
Left port obtains
semaphore
No port accessing
semaphore address
Right port obtains
semaphore
No port accessing
semaphore
Left port obtains
semaphore
No port accessing
semaphore
Power Down
Read Semaphore
I/O Lines Disabled
Write to Semaphore
Read
Write
Illegal Condition
of each other, it is
Operation
CY7C1342
Status
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