PCF8534AHL/1,518 NXP Semiconductors, PCF8534AHL/1,518 Datasheet - Page 16

• Manufacturer Part Number: PCF8534AHL/1,518
• Description: IC LCD DISPLAY DRVR 60SEG 80LQFP
• Manufacturer: NXP Semiconductors

Specifications of PCF8534AHL/1,518

• Package / Case: 80-LQFP
• Display Type: LCD
• Configuration: 60 Segment
• Interface: I²C
• Current - Supply: 8µA
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Digits: 30
• Number Of Segments: 240
• Maximum Clock Frequency: 400 KHz
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 85 C
• Maximum Supply Current: 50 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Digits Or Characters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-5058-2; 935289852518

NXP Semiconductors
PCF8534A_5
Product data sheet
7.5.1 Internal clock
7.5.2 External clock
7.5 Oscillator
7.6 Timing
7.7 Display register
7.8 Segment outputs
The internal logic and the LCD drive signals of the PCF8534A are timed by the frequency
f
f
The internal oscillator is enabled by connecting pin OSC to pin V
output from pin CLK is the clock signal for any cascaded PCF8534A in the system. After
power-on, SDA must be HIGH to guarantee that the clock starts.
Connecting pin OSC to V
external clock input. A clock signal must always be applied to the device, removing the
clock can freeze the LCD in a DC state.
The timing of the PCF8534A organizes the internal data flow of the device. This includes
the transfer of display data from the display RAM to the display segment outputs. In
cascaded applications, the synchronization signal (SYNC) maintains the correct timing
relationship between all the PCF8534As in the system. The timing also generates the
LCD frame frequency which is derived as an integer division of the clock frequency
(see
frequency applied to pad CLK when an external clock is used.
Table 6.
The display register holds the display data while the corresponding multiplex signals are
generated. There is a one-to-one relationship between the data in the display register, the
LCD segment outputs and one column of the display RAM.
The LCD drive section includes 60 segment outputs (S0 to S59) which must be connected
directly to the LCD. The segment output signals are generated based on the multiplexed
backplane signals and with data resident in the display register. When less than
60 segment outputs are required the unused segment outputs must be left open-circuit.
Frame frequency
clk
clk(ext)
f
fr
, which equals either the built-in oscillator frequency f
=
Table
. The clock frequency f
---------
f
24
clk
LCD frame frequencies
6). The frame frequency is a fixed division of the internal clock or of the
Rev. 05 — 6 August 2009
DD
enables an external clock source. Pin CLK becomes the
clk
determines the LCD frame frequency (f
Universal LCD driver for low multiplex rates
Nominal frame frequency (Hz)
64
osc
or the external clock frequency
SS
. In this case, the
PCF8534A
fr
© NXP B.V. 2009. All rights reserved.
).
16 of 47