PCF8534AHL/1,518 NXP Semiconductors, PCF8534AHL/1,518 Datasheet - Page 21

• Manufacturer Part Number: PCF8534AHL/1,518
• Description: IC LCD DISPLAY DRVR 60SEG 80LQFP
• Manufacturer: NXP Semiconductors

Specifications of PCF8534AHL/1,518

• Package / Case: 80-LQFP
• Display Type: LCD
• Configuration: 60 Segment
• Interface: I²C
• Current - Supply: 8µA
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Digits: 30
• Number Of Segments: 240
• Maximum Clock Frequency: 400 KHz
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 85 C
• Maximum Supply Current: 50 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Digits Or Characters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-5058-2; 935289852518

NXP Semiconductors
8. Basic architecture
PCF8534A_5
Product data sheet
8.1.1 Bit transfer
7.15 Blinker
8.1 Characteristics of the I
The display blinking capabilities of the PCF8534A are very versatile. The whole display
can be blinked at frequencies set by the blink select command (see
blinking frequencies are fractions of the clock frequency. The ratios between the clock and
blinking frequencies depend on the mode in which the device is operating (see
Table 7.
Assuming that f
An additional feature is for the arbitrary selection of LCD segments to be blinked. This
applies to the static and 1:2 multiplex drive modes and is implemented without any
communication overheads. Using the output bank selector, the displayed RAM banks are
exchanged with alternate RAM banks at the blinking frequency. This mode can also be
specified by the blink select command.
In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of
LCD segments can be blinked by selectively changing the display RAM data at fixed time
intervals.
If the entire display needs to be blinked at a frequency other than the nominal blinking
frequency, this can be done using the mode set command to set and reset the display
enable bit E at the required rate (see
The I
modules. The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). When
connected to the output stages of a device, both lines must be connected to a positive
supply via a pull-up resistor. Data transfer is initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse. Changes in the data line at this time will
be interpreted as a control signal. Bit transfer is illustrated in
Blink mode
Off
1
2
3
2
C-bus provides bidirectional, two-line communication between different ICs or
Blink frequencies
clk
= 1536 Hz.
Rev. 05 — 6 August 2009
Operating mode ratio
-
f
f
f
blink
blink
blink
2
C-bus
=
=
=
---------
----------- -
1536
----------- -
3072
768
f
f
f
clk
clk
clk
Table
Universal LCD driver for low multiplex rates
10).
Blink frequency
Blinking off
2 Hz
1 Hz
0.5 Hz
Figure
PCF8534A
13.
Table
© NXP B.V. 2009. All rights reserved.
14). The
Table
21 of 47
7).