PCF8534AHL/1,518 NXP Semiconductors, PCF8534AHL/1,518 Datasheet - Page 23

• Manufacturer Part Number: PCF8534AHL/1,518
• Description: IC LCD DISPLAY DRVR 60SEG 80LQFP
• Manufacturer: NXP Semiconductors

Specifications of PCF8534AHL/1,518

• Package / Case: 80-LQFP
• Display Type: LCD
• Configuration: 60 Segment
• Interface: I²C
• Current - Supply: 8µA
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Digits: 30
• Number Of Segments: 240
• Maximum Clock Frequency: 400 KHz
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 85 C
• Maximum Supply Current: 50 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Digits Or Characters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-5058-2; 935289852518

NXP Semiconductors
PCF8534A_5
Product data sheet
8.1.3 Acknowledge
8.1.4 PCF8534A I
8.1.5 Input filters
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
Acknowledgement on the I
The PCF8534A acts as an I
transmit data to an I
the acknowledge signals of the selected devices. Device selection depends on the
I
In single device application, the hardware subaddress inputs A0, A1 and A2 are normally
tied to V
A0, A1 and A2 are tied to V
devices with a common I
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
2
Fig 16. Acknowledgement of the I
•
•
•
•
C-bus slave address, the transferred command data and the hardware subaddress.
A slave receiver which is addressed must generate an acknowledge after the
reception of each byte.
A master receiver must generate an acknowledge after the reception of each byte that
has been clocked out of the slave transmitter.
The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
A master receiver must signal an end-of-data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
master receiver must leave the data line HIGH during the 9th pulse to not
acknowledge. The master will now generate a STOP condition.
by transmitter
SS
data output
by receiver
data output
SCL from
which defines the hardware subaddress 0. In multiple device applications
master
2
C-bus controller
2
condition
C-bus master receiver. The only data output from the PCF8534A are
START
Rev. 05 — 6 August 2009
S
2
C-bus slave address have the same hardware subaddress.
2
SS
C-bus is illustrated in
2
C-bus slave receiver. It does not initiate I
or V
DD
2
1
C-bus
using a binary coding scheme so that no two
Universal LCD driver for low multiplex rates
2
Figure
16.
not acknowledge
acknowledge
8
PCF8534A
acknowledgement
2
clock pulse for
C-bus transfers or
© NXP B.V. 2009. All rights reserved.
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