PCF8534AHL/1,518 NXP Semiconductors, PCF8534AHL/1,518 Datasheet - Page 8

• Manufacturer Part Number: PCF8534AHL/1,518
• Description: IC LCD DISPLAY DRVR 60SEG 80LQFP
• Manufacturer: NXP Semiconductors

Specifications of PCF8534AHL/1,518

• Package / Case: 80-LQFP
• Display Type: LCD
• Configuration: 60 Segment
• Interface: I²C
• Current - Supply: 8µA
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Digits: 30
• Number Of Segments: 240
• Maximum Clock Frequency: 400 KHz
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 85 C
• Maximum Supply Current: 50 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Digits Or Characters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-5058-2; 935289852518

NXP Semiconductors
PCF8534A_5
Product data sheet
7.1 Power-on reset
7.2 LCD bias generator
7.3 LCD voltage selector
The host microprocessor or microcontroller maintains the 2-line I
channel with the PCF8534A.
Biasing voltages for the multiplexed LCD waveforms are generated internally, removing
the need for an external bias generator. The internal oscillator is selected by connecting
pin OSC to V
power supplies (pins V
At power-on the PCF8534A resets to a default starting condition:
Do not transfer data on the I
action to complete.
Fractional LCD biasing voltages are obtained from an internal voltage divider of three
series resistors connected between pins V
of the circuit to provide the
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by the
mode-set command (see
Fig 5.
•
•
•
•
•
•
•
•
All backplane outputs are set to V
All segment outputs are set to V
The selected drive mode is: 1:4 multiplex with
Blinking is switched off
Input and output bank selectors are reset
The I
The data pointer and the subaddress counter are cleared (set to logic 0)
The display is disabled
V
V
DD
SS
2
Typical system configuration
C-bus interface is initialized
CONTROLLER
PROCESSOR/
MICRO-
MICRO-
SS
HOST
. The only other connections required to complete the system are the
R
2C
t
r
b
DD
Rev. 05 — 6 August 2009
, V
Table
1
SS
2
2
C-bus after a power-on for at least 1 ms to allow the reset
bias voltage level for the 1:2 multiplex configuration.
and V
10) from the command decoder. The biasing
OSC
SDA
SCL
LCD
LCD
LCD
A0
) and the LCD panel selected for the application.
LCD
PCF8534A
Universal LCD driver for low multiplex rates
A1
V
DD
and V
A2
V
1
LCD
SA0
3
SS
bias
. The center resistor is switched out
V
SS
60 segment drives
4 backplanes
2
C-bus communication
PCF8534A
© NXP B.V. 2009. All rights reserved.
LCD PANEL
(up to 240
elements)
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