CS5460A-BSZ Cirrus Logic Inc, CS5460A-BSZ Datasheet - Page 9

• Manufacturer Part Number: CS5460A-BSZ
• Description: IC ENERGY METERING 1PHASE 24SSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5460A-BSZ

• Package / Case: 24-SSOP
• Input Impedance: 30 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 0.8V
• Voltage - I/o Low: 0.2V
• Current - Supply: 2.9mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Meter Type: Single Phase
• Output Voltage Range: 2.4 V to 2.6 V
• Output Current: 1 uA
• Input Voltage Range: 2.4 V to 2.6 V
• Input Current: 25 nA
• Power Dissipation: 500 mW
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Ic Function: Single Phase Bi-directional Power / Energy IC
• Brief Features: On-Chip Functions, AC Or DC System Calibration, Power Supply Monitor
• Supply Voltage Range: 3.3V To 5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CDB5460AU - EVALUATION BOARD FOR CS5460A
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1094-5

SWITCHING CHARACTERISTICS
(T
Logic 0 = 0.0 V, Logic 1 = VD+; CL = 50 pF))
Notes: 24. Device parameters are specified with a 4.096 MHz clock, yet, clocks between 3 MHz to 20 MHz can be
DS487F4
Master Clock FrequencyCrystal/Internal Gate Oscillator (Note 24)
Master Clock Duty Cycle
CPUCLK Duty Cycle
Rise Times
Fall Times
Start-up
Oscillator Start-Up Time
Serial Port Timing
Serial Clock Frequency
Serial Clock
SDI Timing
CS Falling to SCLK Rising
Data Set-up Time Prior to SCLK Rising
Data Hold Time After SCLK Rising
SCLK Falling Prior to CS Disable
SDO Timing
CS Falling to SDI Driving
SCLK Falling to New Data Bit
CS Rising to SDO Hi-Z
Auto-boot Timing
Serial Clock
MODE setup time to RESET Rising
RESET rising to CS falling
CS falling to SCLK rising
SCLK falling to CS rising
CS rising to driving MODE low (to end auto-boot sequence).
SDO guaranteed setup time to SCLK rising
A
= -40 °C to +85 °C; VA+ = 5.0 V ±10%; VD+ = 3.0 V ±10% or 5.0 V ±10%; VA- = 0.0 V; Logic Levels:
25. If external MCLK is used, then duty cycle must be between 45% and 55% to maintain this specification.
26. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.
27. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
used. However, for input frequencies over 5 MHz, an external oscillator must be used.
external clock source.
Any Digital Input Except SCLK (Note 26)
Any Digital Input Except SCLK (Note 26)
Parameter
XTAL = 4.096 MHz (Note 27)
Any Digital Output
Any Digital Output
Pulse Width High
Pulse Width High
Pulse Width Low
Pulse Width Low
(Note 25)
SCLK
SCLK
Symbol
MCLK
SCLK
t
t
t
t
t
t
t
t
t
t
t
rise
fall
ost
t
t
t
t
t
t
t
t
t
10
12
13
14
15
16
17
11
1
2
3
4
5
6
7
8
9
Min
200
200
100
100
100
100
2.5
40
50
50
50
48
50
40
-
-
-
-
-
-
-
-
-
-
-
4.096
Typ
50
50
60
20
20
20
16
8
8
8
-
-
-
-
-
-
-
-
-
-
-
-
CS5460A
Max
100
100
1.0
1.0
20
60
60
50
50
50
2
-
-
-
-
-
-
-
-
-
MCLK
MCLK
MCLK
MCLK
MCLK
MHz
MHz
Unit
ms
µs
µs
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
9