MAX16070ETL+ Maxim Integrated Products, MAX16070ETL+ Datasheet - Page 40

• Manufacturer Part Number: MAX16070ETL+
• Description: IC SYSTEM MANAGER 12CH 40-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX16070ETL+

• Applications: Power Supply Monitor
• Voltage - Supply: 2.8 V ~ 14 V
• Current - Supply: 4.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VQFN Exposed Pad, 40-HVQFN, 40-SQFN, 40-DHVQFN
• Product: Current Monitors
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Accuracy: 2.5 %
• Sense Voltage (max): 14 V
• Supply Current (max): 14 mA
• Supply Voltage (max): 14 V
• Supply Voltage (min): 2.8 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Exit1-IR: A rising edge on TCK with TMS low puts the
controller in the pause-IR state. If TMS is high on the
rising edge of TCK, the controller enters the update-IR
state.
Pause-IR: Shifting of the instruction shift register halts
temporarily. With TMS high, a rising edge on TCK puts
the controller in the exit2-IR state. The controller remains
in the pause-IR state if TMS is low during a rising edge
on TCK.
Exit2-IR: A rising edge on TCK with TMS high puts the
controller in the update-IR state. The controller loops
back to shift-IR if TMS is low during a rising edge of TCK
in this state.
Update-IR: The instruction code that has been shifted
into the instruction shift register latches to the parallel
outputs of the instruction register on the falling edge of
TCK as the controller enters this state. Once latched,
this instruction becomes the current instruction. A rising
edge on TCK with TMS low puts the controller in the run-
test/idle state. With TMS high, the controller enters the
select-DR-scan state.
The instruction register contains a shift register as well
as a latched 5-bit-wide parallel output. When the TAP
controller enters the shift-IR state, the instruction shift
Table
Table
40
MSB
BYPASS
IDCODE
USERCODE
LOAD ADDRESS
READ DATA
WRITE DATA
REBOOT
SAVE
SETFLSHADD
RSTFLSHADD
SETUSRFLSH
RSTUSRFLSH
MAX16070
MAX16071
INSTRUCTION
_____________________________________________________________________________________
23. JTAG Instruction Set
24. 32-Bit Identification Code
VERSION
REV
REV
CODE
0x0A
0x0B
0x0C
0x1F
0x00
0x03
0x04
0x05
0x06
0x07
0x08
0x09
PART NUMBER (16 BITS)
1000000000000011
1000000000000100
Instruction Register
Mandatory instruction code
Load manufacturer ID code/part number
Load user code
Load address register content
Read data pointed by current address
Write data pointed by current address
Reboot FLASH data content into register file
Trigger emergency save to flash
Flash page access ON
Flash page access OFF
User flash access ON (must be in flash page already)
User flash access OFF (return to flash page)
MANUFACTURER (11 BITS)
register connects between TDI and TDO. While in the
shift-IR state, a rising edge on TCK with TMS low shifts
the data one stage toward the serial output at TDO. A
rising edge on TCK in the exit1-IR state or the exit2-IR
state with TMS high moves the controller to the update-
IR state. The falling edge of that same TCK latches the
data in the instruction shift register to the instruction reg-
ister parallel output. Table 23 shows the instructions sup-
ported by the MAX16070/MAX16071 and the respective
operational binary codes.
BYPASS: When the BYPASS instruction is latched into
the instruction register, TDI connects to TDO through the
1-bit bypass test data register. This allows data to pass
from TDI to TDO without affecting the device’s operation.
IDCODE: When the IDCODE instruction is latched into the
parallel instruction register, the identification data register
is selected. The device identification code is loaded into
the identification data register on the rising edge of TCK
following entry into the capture-DR state. Shift-DR can be
used to shift the identification code out serially through
TDO. During test-logic-reset, the IDCODE instruction
is forced into the instruction register. The identification
code always has a ‘1’ in the LSB position. The next 11 bits
identify the manufacturer’s JEDEC number and number
of continuation bytes followed by 16 bits for the device
and 4 bits for the version. See Table 24.
00011001011
00011001011
NOTES
FIXED VALUE (1 BIT)
1
1
LSB