ISL8120CRZ Intersil, ISL8120CRZ Datasheet
ISL8120CRZ
Specifications of ISL8120CRZ
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ISL8120CRZ Summary of contents
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... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL8120 ...
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... PART RANGE (Note) MARKING (°C) ISL8120CRZ ISL8120 CRZ 0 to +70 ISL8120CRZ-T* ISL8120 CRZ 0 to +70 ISL8120IRZ ISL8120 IRZ - QFN ISL8120IRZ-T* ISL8120 IRZ - QFN * Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach ...
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Block Diagram REFERENCE V = 0.6V REF VCC 700mV FB1 COMP1 VSEN1+ VSEN1- UNITY GAIN DIFF AMP1 VMON1 EN/FF1 VCC PVCC POWER-ON RESET (POR) OTP OVER-TEMPERATURE PROTECTION (OTP) CHANNEL 1 SOFT-START AND FAULT LOGIC V SAW1 REF AVG_OCP + ∑ ...
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Block Diagram (Continued) RELATIVE PHASE CONTROL k*VDDQ V REF VCC 700mV FB2 COMP2 V REF VSEN2+ VSEN2- UNITY GAIN DIFF AMP2 VMON2 EN/FF2 CLKOUT/REFIN OTP POR MASTER CLOCK OSCILLATOR GENERATOR CHANNEL 2 SOFT-START AND FAULT LOGIC V REF2 SAW2 M/D ...
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Typical Application I (Dual Regulators with DCR Sensing and Remote Sense) VIN +3.3 TO +22V C F2 VIN C F3 ISL8120 CLKOUT/REFIN VCC PGOOD R FS FSYNC EN2/FF2 EN1/FF1 R SET ISET ISHARE 5 ISL8120 VIN_F ...
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Typical Application II (Double Data Rate I or II) VIN +3.3 TO +22V C F2 VIN FSYNC ISL8120 V DDQ R*(VTT/0.6-1) (See notes below) CLKOUT/REFIN 1nF R (Or tie REFIN pin to VMON1 pin) PGOOD R ...
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Typical Application III (2-Phase Operation with r VIN +3V TO +22V VIN C F3 EN/FF1 SET ISET ISHARE PGOOD R FS FSYNC CLKOUT/REFIN FB2 GND VSEN2+ 7 ISL8120 DS(ON VCC ...
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Typical Application IV (3-Phase Regulator with Precision Resistor Sensing) VIN +3V TO +22V C F3 GND VCC C F3 VIN_F C BOOT3 Q3 L OUT3 Q4 R VCC ISEN3 GND VCC 8 ISL8120 L R VCC PVCC ...
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Typical Application V (4 Phase Operation with DCR Sensing) VIN +3V TO +22V PGOOD EN/FF1, 2 VSEN1, 2+ VCC VCC VCC VSEN1,2- VIN_F BOOT2 C BOOT4 UGATE2 Q3 L OUT4 PHASE2 Q4 LGATE2 ISEN2A ISEN2B R ...
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Typical Application VI (3-Phase Regulator with Resistor Sensing and 1 Phase Regulator) +3V to +22V C F3 VIN_F C BOOT4 L OUT4 V OUT2 C OUT2 10Ω FB2 ISEN4 10Ω V SENSE2+ V SENSE2 VIN_F C ...
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Typical Application VIII (Multiple Power Modules in Parallel with Current Sharing Control) VIN +3V to +22V PGOOD CLKOUT/REFIN EN/FF1, 2 VIN BOOT2 C BOOT4 UGATE2 Q7 L OUT4 PHASE2 Q8 LGATE2 Ω 2k ISEN2A R ISEN4 ...
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Typical Application VII (6 Phase Operation with DCR Sensing) VIN +3V TO +22V EN/FF1, 2 PGOOD GND VSEN2+ VSEN2- VCC VIN_F BOOT2 C BOOT6 UGATE2 Q3 L OUT6 PHASE2 Q4 LGATE2 ISEN2A ISEN2B R ISEN6 C ...
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Typical Application VIIII (4 Outputs Operation with DCR Sensing) VIN +3V TO +22V EN/FF2 V SENSE4+ R FB4 VSEN2+ C SEN4 R VSEN2- OS4 VMON2 V SENSE4- Z FB3 COMP2 Z COMP4 2Ω PGOOD 2Ω VIN_F ...
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... 0V, PVCC = 5V PVCC 0V, VCC = 3V VCC I PVCC = 4V TO 5.6V PVCC PVCC = P-Channel MOSFET (VIN = 5V) LDO PVCC I = 0mA to 250mA PVCC ISL8120CRZ ISL8120IRZ t After PLL, VCC, and PVCC PORs, and SS_DLY EN(s) above their thresholds I EN_HYS θ θ (°C/W) (°C/ 3.5 MIN MAX (Note 4) ...
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... VCC = 3.5V to 5.5V RAMP EN Δ 0V; VCC < 3.4V RAMP EN V RAMP_OS VCC = 5.4V (2.97V) VCC = 5.4V (2.97V MIN_OFF t BLANKING V ISL8120CRZ REF1 ISL8120IRZ V ISL8120CRZ REF2 ISL8120IRZ R = 10k 100pF, at COMP Pin L L UGBW_EA R = 10k 100pF, at COMP Pin L L VCC = 5V SR_EA R = 10k 100pF, at COMP Pin ...
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... Sink Current UGATE R 45mA Source Current LGATE R 45mA Sink Current LGATE I VCC = 2.97V to 5.6V SOURCE I VCC = 5V; ISL8120CRZ SOURCE VCC = 5V; ISL8120IRZ VCC = 2.97V to 5.6V V OC_SET (comparator offset included) V VCC = 2.97V to 5.6V OC_SET_HYS (comparator offset included) VCC = 2.97V and 3.6V, 1% Resistor Sense, 10mV Signal VCC = 4 ...
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Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. (Continued) PARAMETER Maximum Sinking Current (Note 3) OVERVOLTAGE PROTECTION OV Latching Up Trip Point OV Non-Latching Up Trip Point (Note 3) LGATE Release Trip Point OVER-TEMPERATURE PROTECTION Over-Temperature Trip (Note 3) Over-Temperature ...
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Functional Pin Descriptions GND (Pin 33) The bottom pad is the signal and power ground plane. All voltage levels are referenced to this pad. This pad provides a return path for the low-side MOSFET drives and internal power circuitries as ...
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It sources 15µA offset current plus the average current of both channels in multiphase mode or Channel 1’s current in independent mode. The share bus (ISHARE pins connected together) voltage (V an external resistor (R ) represents the ...
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VSEN1- resistor is 100Ω and it should not be large in order to keep the unit gain amplifier input impedance compatibility. VMON1, VMON2 (Pins 31, 11) These pins are outputs of the unity gain amplifiers. They are connected internally to ...
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INPUT OUTPUT; I/O = INPUT AND OUTPUT, Bi-DIRECTION) EN1/ EN2/ FF1 FF2 VSEN2- MODE (I) (I) (I) FB2 ( ACTIVE ACTIVE ACTIVE ...
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D ST CH1 UG (1 IC) ST CH2 UG (1 IC) ST CLKOUT (1 IC) 90° ND CH1 UG (2 IC) ND CH2 CH1 UG (1 IC) ST CH2 UG (1 IC) ST CLKOUT (1 ...
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Functional Description Initialization Initially, the ISL8120 Power-On Reset (POR) circuits continually monitor the bias voltages (PVCC and VCC) and the voltage at the EN pin. The POR function initiates soft-start operation 384 clock cycles after the EN pin voltage is ...
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VIN ISL8120 R UP 2-PHASE EN/FF1 EN/FF1 EN/FF2 EN/FF2 R DOWN V EN_HYS R = --------------------------------------------------------- - ⋅ EN_HYS PHASE FIGURE 6. TYPICAL 4-PHASE WITH FAULT HANDSHAKE While EN/FF is pulled to ground, a constant voltage (0.8V) ...
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VMON1 113% 87% OR EN/FF1 VMON1>120% OR multiphase MODE = HIGH VMON2 113% 87% OR EN/FF2 VMON2 > 120% FIGURE 11. FORCE LGATE HIGH LOGIC Both channels share the same PGOOD output. Either of the channels indicating out-of-regulation will pull-down ...
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Current Loop When the ISL8120 operates in 2-phase mode, the current control loop keeps the channel’s current in balance. After 175ns blanking period with respect to the falling edge of the PWM pulse of each channel, the voltage developed across ...
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The signal I is then subtracted from the individual AVG channel’s scaled current ( CS1 CS2 correction signal for each channel. The current correction signal keeps each channel’s output current contribution balanced relative to the other active channel. ...
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For multiphase implementation, one single error amplifier should be used for the voltage loop. Therefore, all other channels’ error amplifiers should be disabled with their corresponding VSEN- pulled to VCC, as shown in Figure 16. Current Share Control Loop in ...
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VSEN1/2- COM1/2 ISET 1 ISL8120 R ISHARE ISET1 R ISHARE1 FIGURE 16. SIMPLIFIED 6-PHASE SINGLE OUTPUT IMPLEMENTATION The second option for multi-module parallel system is to have only one signal (ISHARE) wire connection. The signal wire connection scheme is targeted ...
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ITRIP = 108µA; IOC is the load overcurrent trip point the minimum Ugate turn off time that is 350ns; MIN_OFF R in Equation 6 represents the total equivalent ISHARE resistance in ISHARE pin bus of all ICs in ...
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DR_UP DR_LOW ⎛ HI1 LO1 ⎜ -------------------------------------- + --------------------------------------- - DR_UP ⎝ HI1 EXT1 LO1 EXT1 ⎛ HI2 LO2 ⎜ -------------------------------------- --------------------------------------- ...
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Differential Amplifier for Remote Sense VSEN+ 20k R = 500k DIF 20k VSEN- 20k FIGURE 22. EQUIVALENT DIFFERENTIAL AMPLIFER The differential remote sense buffer has a precision unity gain resistor matching network, which has a ultra low offset of 1mV. ...
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VSENSE- (REMOTE) 10Ω VOUT (LOCAL) GND (LOCAL) 10Ω VCC VSEN- 700mV FIGURE 24. SIMPLIFIED REMOTE SENSING IMPLEMENTATION Since the UV/OV comparator uses the same internal reference 0.6V, to guarantee UV/OV and Pre-charged start-up functions of Channel 2, the target voltage ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
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Package Outline Drawing L32.5x5B 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 11/07 5.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( 4. 80 TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 35 ISL8120 A ...