ISL8120CRZ Intersil, ISL8120CRZ Datasheet - Page 32

• Manufacturer Part Number: ISL8120CRZ
• Description: IC CTRLR PWM 2PHASE W/DVR 32-QFN
• Manufacturer: Intersil

Specifications of ISL8120CRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 2
• Frequency - Max: 1.5MHz
• Duty Cycle: 90%
• Voltage - Supply: 3 V ~ 22 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Frequency-max: 1.5MHz
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Differential Amplifier for Remote Sense
The differential remote sense buffer has a precision unity
gain resistor matching network, which has a ultra low offset
of 1mV. This true remote sensing scheme helps compensate
the droop due to load on the positive and negative rails and
maintain the high system accuracy of ±0.6%.
The output of the remote sense buffer is connected directly
to the internal OV/UV comparator. As a result, a resistor
divider should be placed on the input of the buffer for proper
regulation, as shown in Figure 24. The VMON pin should be
connected to the FB pin by a standard feedback network.
Since the input impedance of VSEN+ pin in respect to
VSEN- pin is about 500kΩ, it is highly recommended to
include this impedance into calculation and use 100Ω or less
for the lower leg (R
optimize system accuracy. Note that any RC filter at the
inputs of the differential amplifier will contribute as a pole to
the overall loop compensation.
FIGURE 22. EQUIVALENT DIFFERENTIAL AMPLIFER
VSEN-
R
VSEN+
DIF
= 500k
OS
FIGURE 23. DUAL OUTPUT VOLTAGE SENSE FOR SINGLE POINT OF FAILURE PROTECTION
) of the feedback resistor divider to
700mV
VCC
32
R
20k
FB
20k
20k
VSEN+
VOUT
R
OS
20k
VSEN-
GAIN=1
GND
R
V
VMON
OS
REF
ISL8120
R
FB
OV/UV
COMP
As some applications will not need the differential remote
sense, the output of the remote sense buffer can be disabled
and be placed in high impedance by pulling VSEN- within
700mV of VCC. In such an event, the VMON pin can be
used as an additional monitor of the output voltage with a
resistor divider to protect the system against single point of
failure, which occurs in the system using the same resistor
divider for the UV/OV comparator and the output regulation.
The resistor divider ratio should be the same as the one for
the output regulation so that the correct voltage information
is provided to the OV/UV comparator. Figure 23 shows the
differential sense amplifier can be directly used as a monitor
without pulling VSEN- high.
DDR and Dual Mode Operation
If the CLKOUT/REFIN is less than 800mV, an external
soft-start ramp (0.6V) can be in parallel with the Channel 2’s
internal soft-start ramp for DDR/tracking applications (DDR
Mode).
The output voltage (typical VTT output) of Channel 2 tracks
with the input voltage (typical VDDQ*(1+k) from Channel 1)
at the CLKOUT/REFIN pin. As for the external input signal
and internal reference signal (ramp and 0.6V), the one with
the lowest voltage will be the one to be used as the
reference comparing with FB signal. So in DDR
configuration, VTT channel should start-up later after its
internal soft-start ramp in which way the VTT will track the
voltage on REFIN pin derived from VDDQ. This can be
achieved by adding more filtering at EN//FF1 compared with
EN/FF2.
FB
Z
ERROR AMP
COMP
COMP
PGOOD
PGOOD
March 20, 2009
FN6641.0