ISL8120CRZ Intersil, ISL8120CRZ Datasheet - Page 33

• Manufacturer Part Number: ISL8120CRZ
• Description: IC CTRLR PWM 2PHASE W/DVR 32-QFN
• Manufacturer: Intersil

Specifications of ISL8120CRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 2
• Frequency - Max: 1.5MHz
• Duty Cycle: 90%
• Voltage - Supply: 3 V ~ 22 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Frequency-max: 1.5MHz
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Since the UV/OV comparator uses the same internal reference
0.6V, to guarantee UV/OV and Pre-charged start-up functions
of Channel 2, the target voltage derived from Channel 1
(VDDQ) should be scaled close to 0.6V, and it is suggested to
be slightly above (+2%) 0.6V with an external resistor divider,
which will have Channel 2 use the internal 0.6V reference after
soft-start. Any capacitive load at REFIN pin should not slow
down the ramping of this input 150mV lower than the Channel
2’ internal ramp. Otherwise, the UV protection could be fault
triggered prior to the end of the soft-start. The start-up of
Channel 2 can be delayed to avoid such situation happening, if
high capacitive load presents at REFIN pin for noise
decoupling. During shutdown, Channel 2 will follow Channel 1
until both channels drops below 87%, at which point both
channels enter UV protection zone. Depending on the loading,
Channel 1 might drop faster than Channel 2. To solve this race
condition, Channel 2 can either power up from Channel 1 or
bridge the Channel 1 with a high current Schottky diode. If the
system requires to shutdown both channels when either has a
fault, tying EN/FF1 and EN/FF2 will do the job. In DDR mode,
Channel 1 delays 60° over Channel 2.
In Dual mode, depending upon the resistor divider level of
REFIN from VCC, the ISL8120 operates as a dual-PWM
controller for two independent regulators with a phase shift,
as shown in Table 2. The phase shift is latched as VCC
raises above POR and cannot be changed on the fly.
MODE
DDR
Dual
Dual
Dual
29% to 45% of VCC
45% to 62% of VCC
REFIN RANGE
VOUT (LOCAL)
GND (LOCAL)
<29% of VCC
DECODING
62% to VCC
700mV
VCC
TABLE 2.
VSENSE- (REMOTE)
10Ω
PHASE for CHANNEL
10Ω
2 WRT CHANNEL 1
33
FIGURE 24. SIMPLIFIED REMOTE SENSING IMPLEMENTATION
180°
-60°
90°
0°
VSEN-
C
SEN
R
OS
VSEN+
R
GAIN=1
FB
VSENSE+ (REMOTE)
REQUIRED
37% VCC
53% VCC
REFIN
VCC
0.6V
V
VMON
REF
ISL8120
Z
FB
OV/UV
COMP
Internal Reference and System Accuracy
The internal reference is set to 0.6V. Including bandgap
variation and offset of differential and error amplifiers, it has
an accuracy of ±0.6% over commercial temperature range,
and 0.9% over industrial temperature range. While the
remote sense is not used, its offset (V
included in the tolerance calculation. Equations 9 and 10
show the worst case of system accuracy calculation.
V
in the loop, the differential amplifier’s input impedance
(R
and can be neglected when R
precision setpoint, R
resistors.
Figure 26 shows the tolerance of various output voltage
regulation for 1%, 0.5%, and 0.1% feedback resistor
OS_DA
k*R
DIF
R
VDDQ
) is typically 500kΩ with a tolerance of 20% (RDIF%)
FB
FIGURE 25. SIMPLIFIED DDR IMPLEMENTAION
should set to zero when the differential amplifier is
Z
ERROR AMP
COMP
Internal SS
PHASE-SHIFTED
CLKOUT/REFIN
k
CLOCK
=
VTT
------------ 1
0.6V
COMP
OS
–
can be scaled by two paralleled
PGOOD
OS
0.6V
FB2
is less than 100Ω. To set a
PGOOD
VCC
700mV
OS_DA
VSEN2-
) should be
MACHINE
March 20, 2009
E/A2
ISL8120
STATE
FN6641.0