ADP3211AMNR2G ON Semiconductor, ADP3211AMNR2G Datasheet - Page 29

• Manufacturer Part Number: ADP3211AMNR2G
• Description: IC CTLR BUCK 7BIT 2PHASE 32QFN
• Manufacturer: ON Semiconductor

Specifications of ADP3211AMNR2G

• Applications: Controller, Power Supplies for Next-Generation Intel Processors
• Voltage - Input: 3.3 ~ 22 V
• Number Of Outputs: 1
• Voltage - Output: 0.0125 ~ 1.5 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 32-TFQFN Exposed Pad
• Output Voltage: 1.1 V
• Output Current: 10 A
• Input Voltage: 19 V
• Supply Current: 6 mA
• Switching Frequency: 400 KHz
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Set the AC Load Line
7. Measure the output ripple with no load and with a
1. Remove the dc load from the circuit and connect
2. Connect the scope to the output voltage and set it
3. Set the dynamic load for a transient step of about
4. Measure the output waveform (note that use of a
5. The resulting waveform will be similar to that
6. If the difference between V
7. Repeat Steps 5 and 6 until no adjustment of C
8. Set the dynamic load step to its maximum step
full load with scope, making sure both are within
the specifications.
a dynamic load.
to dc coupling mode with a time scale of
100 ms/div.
40 A at 1 kHz with 50% duty cycle.
dc offset on the scope may be necessary to see the
waveform). Try to use a vertical scale of
100 mV/div or finer.
shown in Figure 37. Use the horizontal cursors to
measure V
Figure 37. Do not measure the undershoot or
overshoot that occurs immediately after the step.
more than a couple of millivolts, use Equation 47
to adjust C
parallel values to obtain an adequate one because
there are limited standard capacitor values
available (it is a good idea to have locations for
two capacitors in the layout for this reason).
is needed. Once this is achieved, do not change
C
size (but do not use a step size that is larger than
needed) and verify that the output waveform is
square, meaning V
C
CS
CS(NEW)
Figure 37. AC Load Line Waveform
for the rest of the procedure.
+ C
ACDRP
CS
. It may be necessary to try several
CS(OLD)
and V
ACDRP
DCDRP
V
V
V
and V
ACDRP
DCDRP
ACDRP
ACDRP
, as shown in
DCDRP
and V
V
are equal.
DCDRP
DCDRP
(eq. 47)
http://onsemi.com
CS
is
29
Set the Initial Transient
Figure 38. Transient Setting Waveform, Load Step
a. Increase the resistance of the ramp resistor
b. For V
c. For V
9. Ensure that the load step slew rate and the
1. With the dynamic load set at its maximum step
2. If both overshoots are larger than desired, try the
3. For load release (see Figure 39), if V
powerup slew rate are set to ~150 A/ms to
250 A/ms (for example, a load step of 10 A should
take 50 ns to 100 ns) with no overshoot. Some
dynamic loads have an excessive overshoot at
powerup if a minimum current is incorrectly set
(this is an issue if a VTT tool is in use).
size, expand the scope time scale to 2 ms/div to
5 ms/div. This results in a waveform that may
have two overshoots and one minor undershoot
before achieving the final desired value after
V
following adjustments in the order shown.
If these adjustments do not change the response, it
is because the system is limited by the output
decoupling. Check the output response and the
switching nodes each time a change is made to
ensure that the output decoupling is stable.
larger than the value specified by IMVP−6.5, a
greater percentage of output capacitance is
needed. Either increase the capacitance directly
or decrease the inductor values. (If inductors are
changed, however, it will be necessary to
redesign the circuit using the information from
the spreadsheet and to repeat all tuning guide
procedures).
V
DROOP
TRAN1
(R
switching frequency.
C
A
RAMP
TRAN1
TRAN2
by 25%.
(see Figure 38).
V
) by 25%.
TRAN2
, increase R
, increase C
V
DROOP
A
B
or increase the
by 25% and decrease
TRANREL
is