MAX1715EEI Maxim Integrated Products, MAX1715EEI Datasheet - Page 19

• Manufacturer Part Number: MAX1715EEI
• Description: IC CTRLR DC DUAL STPDWN 28-QSOP
• Manufacturer: Maxim Integrated Products
• Type: Step-Down (Buck)r

Specifications of MAX1715EEI

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 2
• Voltage - Output: 1V, 1.8V, 2.5V, 3.3V, Adj
• Current - Output: 8A
• Frequency - Switching: 200kHz, 300kHz, 420kHz, 540kHz
• Voltage - Input: 2 ~ 28 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-QSOP
• Power - Output: 640mW
• Output Voltage: 1 V to 5.5 V, 3.3 V, 2.5 V
• Output Current: 8 A
• Input Voltage: 2 V to 28 V
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Case: SSOP
• Dc: 05+
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The amount of overshoot due to stored inductor energy
can be calculated as:
where I
Stability is determined by the value of the ESR zero rel-
ative to the switching frequency. The point of instability
is given by the following equation:
where:
For a typical 300kHz application, the ESR zero frequen-
cy must be well below 95kHz, preferably below 50kHz.
Tantalum and OS-CON capacitors in widespread use
at the time of publication have typical ESR zero fre-
quencies of 15kHz. In the design example used for
inductor selection, the ESR needed to support 50mVp-p
ripple is 50mV/3.5A = 14.2mΩ. Three 470µF/4V Kemet
T510 low-ESR tantalum capacitors in parallel provide
15mΩ max ESR. Their typical combined ESR results in
a zero at 14.1kHz, well within the bounds of stability.
Don’t put high-value ceramic capacitors directly across
the fast feedback inputs (FB_ to AGND) without taking
precautions to ensure stability. Large ceramic capaci-
tors can have a high-ESR zero frequency and cause
erratic, unstable operation. However, it’s easy to add
enough series resistance by placing the capacitors a
couple of inches downstream from the junction of the
inductor and FB_ pin (see the All-Ceramic-Capacitor
Application section).
Unstable operation manifests itself in two related but
distinctly different ways: double-pulsing and fast-feed-
back loop instability.
Double-pulsing occurs due to noise on the output or
because the ESR is so low that there isn’t enough volt-
age ramp in the output voltage signal. This “fools” the
error comparator into triggering a new cycle immedi-
ately after the 400ns minimum off-time period has
expired. Double-pulsing is more annoying than harmful,
resulting in nothing worse than increased output ripple.
However, it can indicate the possible presence of loop
instability, which is caused by insufficient ESR.
Output Capacitor Stability Considerations
PEAK
f
ESR
is the peak inductor current.
=
______________________________________________________________________________________
f
ΔV
2
ESR
×
≈
Ultra-High Efficiency, Dual Step-Down
π
LI
2CV
=
PEAK
×
π
f
OUT
R
Controller for Notebook Computers
1
ESR
2
×
C
F
Loop instability can result in oscillations at the output
after line or load perturbations that can trip the overvolt-
age protection latch or cause the output voltage to fall
below the tolerance limit.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient (refer to the
MAX1715 EV kit manual) and carefully observe the out-
put voltage ripple envelope for overshoot and ringing. It
can help to simultaneously monitor the inductor current
with an AC current probe. Don’t allow more than one
cycle of ringing after the initial step-response under- or
overshoot.
The input capacitor must meet the ripple current
requirement (IRMS) imposed by the switching currents.
Nontantalum chemistries (ceramic, aluminum, or OS-
CON) are preferred due to their resistance to power up
surge currents.
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
(>5A) when using high-voltage (>20V) AC adapters.
Low-current applications usually require less attention.
For maximum efficiency, choose a high-side MOSFET
(Q1) that has conduction losses equal to the switching
losses at the optimum battery voltage (15V). Check to
ensure that the conduction losses at the minimum
input voltage don’t exceed the package thermal limits
or violate the overall thermal budget. Check to ensure
that conduction losses plus switching losses at the
maximum input voltage don’t exceed the package rat-
ings or violate the overall thermal budget.
Choose a low-side MOSFET (Q2) that has the lowest
possible R
age (i.e., SO-8), and is reasonably priced. Ensure that
the MAX1715 DL gate driver can drive Q2; in other
words, check that the gate isn’t pulled up by the high-
side switch turning on due to parasitic drain-to-gate
capacitance, causing cross-conduction problems.
Switching losses aren’t an issue for the low-side MOS-
FET since it’s a zero-voltage switched device when
used in the buck topology.
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET, the worst-case-
I
DS(ON)
RMS
=
, comes in a moderate to small pack-
I
LOAD
MOSFET Power Dissipation
Input Capacitor Selection
Power MOSFET Selection
⎛
⎜
⎜
⎝
V
OUT IN
(
V - V
V
IN
OUT
)
⎞
⎟
⎟
⎠
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