KSZ8993MI Micrel Inc, KSZ8993MI Datasheet
KSZ8993MI
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KSZ8993MI
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KSZ8993MI Summary of contents
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... Fast Ethernet applications. ___________________________________________________________________________________________________ Functional Diagram Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 ( October 2008 Integrated 3-Port 10/100 Managed The KSZ8993M contains two 10/100 transceivers with patented mixed-signal low-power technology, ...
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Micrel, Inc. AUTO MDI/MDI-X AUTO MDI/MDI-X MII/SNI SPI MIIM SMI LED[3:0] P2 LED[3:0] Features • Proven Integrated 3-Port 10/100 Ethernet Switch – 2nd generation switch with three MACs and two PHYs fully compliant to IEEE 802.3u ...
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Micrel, Inc. • Switch Management Features – Port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or MII – MIB counters for fully compliant statistics gathering, 34 MIB counters per port – Loopback modes for remote diagnostic of failure • ...
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... Micrel, Inc. Ordering Information Part Number Pb-Free Standard KSZ8993M KS8993M KSZ8993ML KS8993ML KSZ8993MI KS8993MI KSZ8993MLI KS8993MLI October 2008 Temperature Range 128-Pin PQFP, Lead-free 128-Pin PQFP, Lead-free o o – +85 C 128-Pin PQFP, Lead-free o o – +85 C 128-Pin PQFP, Lead-free 4 KSZ8993M/ML Package M9999-020606 ...
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... Added 25MHz crystal/oscillator clock’s ppm spec. in Pin Description. 2 Updated I C Slave Serial Bus Configuration section. Updated KSZ8993MI availability to from Q1 2004. Added KS8993ML to General Description (page 1) and to the Functional Description. Updated Part Ordering Information table. Updated pin description for pin 22 to the following For KS8993M, this is an input power pin for the 1 ...
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Micrel, Inc. Contents List of Figures .........................................................................................................................................9 List of Tables...........................................................................................................................................9 Pin Description and I/O Assignment...................................................................................................10 Pin Configuration..................................................................................................................................20 Functional Description .........................................................................................................................21 Functional Overview: Physical Layer Transceiver ............................................................................21 100BASE-TX Transmit.........................................................................................................................................................21 100BASE-TX Receive ..........................................................................................................................................................21 PLL Clock Synthesizer........................................................................................................................................................22 Scrambler/De-scrambler (100BASE-TX Only) ...................................................................................................................22 100BASE-FX Operation.......................................................................................................................................................22 ...
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Micrel, Inc. Register 0: MII Basic Control..........................................................................................................................................46 Register 1: MII Basic Status ...........................................................................................................................................46 Register 2: PHYID HIGH ................................................................................................................................................46 Register 3: PHYID LOW.................................................................................................................................................46 Register 4: Auto-Negotiation Advertisement Ability ........................................................................................................47 Register 5: Auto-Negotiation Link Partner Ability ...........................................................................................................47 Register Map: Switch & PHY ...
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Micrel, Inc. Register 43 (0x2B): Port 2 Control 11 ............................................................................................................................59 Register 59 (0x3B): Port 3 Control 11 ............................................................................................................................59 Register 28 (0x1C): Port 1 Control 12 ............................................................................................................................60 Register 44 (0x2C): Port 2 Control 12 ............................................................................................................................60 Register 60 (0x3C): Reserved, not applied ...
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Micrel, Inc. Package Information.............................................................................................................................86 List of Figures Figure 1. Typical Straight Cable Connection .......................................................................................................................................25 Figure 2. Typical Crossover Cable Connection ...................................................................................................................................25 Figure 3. Auto Negotiation and Parallel Operation .............................................................................................................................26 Figure 4. Destination Address Lookup Flow Chart, Stage 1 ..............................................................................................................27 Figure ...
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Micrel, Inc. Pin Description and I/O Assignment Pin Number Pin Name 1 P1LED2 2 P1LED1 3 P1LED0 4 P2LED2 5 P2LED1 6 P2LED0 7 DGND Note: 1. Ipu/O = Input with internal pull-up during reset, output pin otherwise. Gnd = ...
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Micrel, Inc. Pin Number Pin Name 8 VDDIO ADVFC 13 P2ANEN 14 P2SPD 15 P2DPX 16 P2FFC P2LED3 21 DGND 22 VDDC/VOUT_1 V8 23 LEDSEL1 24 ...
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Micrel, Inc. Pin Number Pin Name HWPOVR 28 P2MDIXDIS 29 P2MDIX 30 P1ANEN 31 P1SPD 32 P1DPX 33 P1FFC PWRDN 37 AGND 38 VDDA 39 AGND 40 MUX1 41 MUX2 42 AGND ...
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Micrel, Inc. Pin Number Pin Name 45 RXP1 46 RXM1 47 AGND 48 TXP1 49 TXM1 50 VDDATX 51 VDDARX 52 RXM2 53 RXP2 54 AGND 55 TXM2 56 TXP2 57 VDDA 58 AGND 59 TEST1 60 TEST2 61 ISET ...
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Micrel, Inc. Pin Number Pin Name 70 LEDSEL0 71 SMTXEN 72 SMTXD3 73 SMTXD2 74 SMTXD1 75 SMTXD0 76 SMTXER 77 SMTXC 78 DGND 79 VDDIO 80 SMRXC 81 SMRXDV 82 SMRXD3 83 SMRXD2 84 SMRXD1 85 SMRXD0 86 SCOL ...
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Micrel, Inc. Pin Number Pin Name 88 SCONF1 89 SCONF0 90 DGND 91 VDDC 92 PRSEL1 93 PRSEL0 94 MDC 95 MDIO 96 SPIQ 97 SCL 98 SDA 99 SPIS_N Note Power supply. Gnd = Ground. Ipu ...
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Micrel, Inc. Pin Number Pin Name 100 PS1 101 PS0 102 PV31 103 PV32 Note Input. Ipu = Input w/ internal pull-up. O= Output. Ipd = Input w/ internal pull-down. October 2008 (1) Type Description Ipd Serial ...
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Micrel, Inc. Pin Number Pin Name 104 PV21 105 PV23 106 DGND 107 VDDIO 108 PV12 109 PV13 110 P3_1PEN 111 P2_1PEN 112 P1_1PEN 113 P3_TXQ2 Note Power supply. Gnd = Ground. Ipu = Input w/ internal ...
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Micrel, Inc. Pin Number Pin Name 114 P2_TXQ2 115 P1_TXQ2 116 P3_PP 117 P2_PP 118 P1_PP 119 P3_TAGINS 120 P2_TAGINS Note: 1. Ipd = Input w/ internal pull-down. October 2008 (1) Type Description Ipd Select transmit queue split on port ...
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Micrel, Inc. Pin Number Pin Name 121 P1_TAGINS 122 DGND 123 VDDC 124 P3_TAGRM 125 P2_TAGRM 126 P1_TAGRM 127 TESTEN 128 SCANEN Note Power supply. Gnd = Ground. Ipd = Input w/ internal pull-down. October 2008 (1) ...
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Micrel, Inc. Pin Configuration PV32 PV21 PV23 DGND VDDIO PV12 PV13 P3_1PEN P2_1PEN P1_1PEN P3_TXQ2 P2_TXQ2 P1_TXQ2 P3_PP P2_PP P1_PP P3_TAGINS P2_TAGINS P1_TAGINS DGND VDDC P3_TAGRM P2_TAGRM P1_TAGRM TESTEN SCANEN October 2008 128-Pin PQFP (Top View) 20 KSZ8993M/ML AGND VDDAP ...
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Micrel, Inc. Functional Description The KSZ8993M contains two 10/100 physical layer transceivers and three MAC units with an integrated Layer 2 managed switch. The KSZ8993M has the flexibility to reside in either a managed or unmanaged design managed ...
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Micrel, Inc. PLL Clock Synthesizer The KSZ8993M generates 125MHz, 31.25MHz, 25MHz, and 10MHz clocks for system timing. Internal clocks are generated from an external 25MHz crystal or oscillator. Scrambler/De-scrambler (100BASE-TX Only) The purpose of the scrambler is to spread the ...
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Micrel, Inc. 10BASE-T Transmit The output 10BASE-T driver is incorporated into the 100BASE-T driver to allow transmission with the same magnetic. They are internally wave-shaped and pre-emphasized into outputs with a typical 2.3V amplitude. The harmonic contents are at least ...
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Micrel, Inc. Straight Cable A straight cable connects an MDI device to an MDI-X device MDI-X device to an MDI device. The following diagram depicts a typical straight cable connection between a NIC card (MDI) and a switch, ...
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Micrel, Inc. Crossover Cable A crossover cable connects an MDI device to another MDI device MDI-X device to another MDI-X device. The following diagram shows a typical crossover cable connection between two switches or hubs (two MDI-X devices). ...
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Micrel, Inc. Start Auto Negotiation Force Link Setting Ye s Bypass Auto Negotiation and Set Link Mode October 2008 N Parallel Operation o Attempt Auto Listen for 100BASE-TX Negotiation Idles Join Flow Link Mode Set ? Yes Link Mode Set ...
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Micrel, Inc. Functional Overview: MAC and Switch Address Lookup The internal lookup table stores MAC addresses and their associated information. It contains a 1K uni-cast address table plus switching information. The KSZ8993M is guaranteed to learn 1K addresses and distinguishes ...
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Micrel, Inc. PTF1= NULL Search complete. Get PTF1 from Static MAC Table Search complete. Get PTF1 from Dynamic MAC Table Figure 4. Destination Address Lookup Flow Chart, Stage 1 October 2008 Start - Search VLAN table NO VLAN ID - ...
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Micrel, Inc. Spanning Tree Process IGMP Process Port Mirror Process Port VLAN Membership Check Figure 5. Destination Address Resolution Flow Chart, Stage 2 The KSZ8993M will not forward the following packets: 1. Error packets. These include framing errors, FCS errors, ...
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Micrel, Inc. Switching Engine The KSZ8993M features a high-performance switching engine to move data to and from the MACs’ packet buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency. The KSZ8993M has a ...
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Micrel, Inc. sending out packets and keeps other stations in carrier sense deferred state. If the port has packets to send during a backpressure situation, the carrier sense type back pressure will be interrupted and those packets will be transmitted ...
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Micrel, Inc. The MII interface operates in either PHY mode or MAC mode. The interface is a nibble wide data interfaces and therefore run at ¼ the network bit rate (not encoded). Additional signals on the transmit side indicate when ...
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Micrel, Inc. The MIIM interface consists of the following: A physical connection that incorporates the data line (MDIO) and the clock line (MDC). A specific protocol that operates across the aforementioned physical connection that allows an external controller to communicate ...
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Micrel, Inc. Registers are 8 data bits wide. For read operation, data bits [15:8] are read back as 0’s. For write operation, data bits [15:8] are not defined, and hence can be set to either 0’s or 1’s. SMI register ...
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Micrel, Inc. Software action: The processor should program the “Static MAC table” with the entries that it needs to receive (e.g., BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the ...
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Micrel, Inc. IGMP Support For IGMP support in layer 2, the KSZ8993M provides two components: “IGMP” Snooping The KSZ8993M will trap IGMP packets and forward them only to the processor (port 3). The IGMP packets are identified as IP packets ...
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Micrel, Inc. DA found in Static MAC Use FID flag? Table? No Don’t care No Don’t care Yes 0 Yes 1 Yes 1 Yes 1 FID+SA found in Dynamic MAC Table? No Yes Advanced VLAN features, such as “Ingress VLAN ...
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Micrel, Inc. Port-Based Priority With port based priority, each ingress port can be individually classified as a high priority receiving port. All packets received at the high priority receiving port are marked as high priority, and will be sent to ...
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Micrel, Inc. Rate Limiting Support The KSZ8993M supports hardware rate limiting independently on the “receive side” and on the “transmit side” per port basis. Rate limiting is supported in both priority and non-priority environment. The rate limit starts ...
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Micrel, Inc Enable I C master mode by setting the KSZ8993M strap-in pins, PS[1:0] (pins 100 and 101, respectively) to “00”. 3. Check to ensure that the KSZ8993M reset signal input, RST_N (pin 67), is properly connected to ...
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Micrel, Inc. SPI multiple read is initiated when the master device continues to drive the KSZ8993M SPIS_N input pin (SPI Slave Select signal) low after a byte (a register) is read. The KSZ8993M internal address counter will increment automatically to ...
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Micrel, Inc. SPIS_N SPIC SPID SPIQ WRITE COMMAND SPIS_N SPIC SPID SPIQ READ COMMAND SPIS_N SPIC SPID SPIQ WRITE COMMAND SPIS_N SPIC SPID SPIQ Byte ...
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Micrel, Inc. SPIS_N SPIC SPID SPIQ READ COMMAND SPIS_N SPIC SPID SPIQ Byte 2 October 2008 ...
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Micrel, Inc. Loopback Support The KSZ8993M provides loopback support for remote diagnostic of failure. In loopback mode, the speed at both PHY ports needs to be set to 100BASE-TX, and the “Priority Buffer reserve” bit needs to be set to ...
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Micrel, Inc. MII Management (MIIM) Registers The MIIM interface is used to access the MII PHY registers defined in this section. The SPI, I interfaces can also be used to access these registers. The latter three interfaces use a different ...
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Micrel, Inc. Register 0: MII Basic Control (continued) Bit Name R/W 3 Disable MDIX R/W Disable far end 2 R/W fault 1 Disable R/W transmit 0 Disable LED R/W Register 1: MII Basic Status Bit Name R capable ...
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Micrel, Inc. Register 4: Auto-Negotiation Advertisement Ability Bit Name R/W 15 Next page RO 14 Reserved RO 13 Remote fault RO 12-11 Reserved RO 10 Pause R/W 9 Reserved R/W 8 Adv 100 Full R/W 7 Adv 100 Half R/W ...
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Micrel, Inc. Register Map: Switch & PHY (8 bit registers) Global Registers Register (Decimal) Register (Hex0 0-1 0x00-0x01 2-11 0x02-0x0B 12 0x0C 13-15 0x0D-0x0F Port Registers Register (Decimal) Register (Hex0 16-29 0x10-0x1D 30-31 0x1E-0x1F 32-45 0x20-0x2D 46-47 0x2E-0x2F 48-61 0x30-0x3D ...
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Micrel, Inc. Register 1 (0x01): Chip ID1 / Start Switch Bit Name R/W 7-4 Chip ID RO 3-1 Revision Start switch RW Register 2 (0x02): Global Control 0 Bit Name R/W 7 New back-off R/W Enable 6-4 ...
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Micrel, Inc. Register 3 (0x03): Global Control 1 Bit Name R/W 7 Pass all frames R/W 6 Repeater R/W mode 5 IEEE 802.3x R/W Transmit direction flow control enable 4 IEEE 802.3x R/W Receive direction flow control enable 3 Frame ...
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Micrel, Inc. Register 4 (0x04): Global Control 2 (continued) Bit Name R/W 4 Flow control R/W and back pressure fair mode 3 No excessive R/W collision drop 2 Huge packet R/W support 1 Legal R/W Maximum Packet size check enable ...
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Micrel, Inc. Register 5 (0x05): Global Control 3 (continued) Bit Name R/W 0 Sniff mode R./W select Register 6 (0x06): Global Control 4 Bit Name R/W 7 Reserved R/W 6 Switch MII half- R/W duplex mode 5 Switch MII flow ...
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Micrel, Inc. Register 6 (0x06): Global Control 4 (continued) Bit Name R/W 3 Null VID R/W replacement Broadcast 2-0 R/W storm protection rate Bit [10:8] Register 7 (0x07): Global Control 5 Bit Name R/W 7-0 Broadcast R/W storm protection (1) ...
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Micrel, Inc. Register 11 (0x0B): Global Control 9 (continued) Bit Name R/W Description 2 Reserved R/W Reserved 1 LED mode R/W This register bit sets the LEDSEL0 selection only. LEDSEL1 is set via strap-in pin. Port x LED indicators, defined ...
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Micrel, Inc. Port Registers The following registers are used to enable features that are assigned on a per port basis. The register bit assignments are the same for all ports, but the address for each port is different, as indicated. ...
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Micrel, Inc. Register 16 (0x10): Port 1 Control 0 Register 32 (0x20): Port 2 Control 0 Register 48 (0x30): Port 3 Control 0 (continued) Bit Name R/W 1 Tag removal R/W 0 Priority enable R/W Register 17 (0x11): Port 1 ...
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Micrel, Inc. Register 18 (0x12): Port 1 Control 2 Register 34 (0x22): Port 2 Control 2 Register 50 (0x32): Port 3 Control 2 Bit Name R/W 7 Reserved 6 Ingress VLAN R/W filtering 5 Discard non R/W PVID packets 4 ...
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Micrel, Inc. Register 20 (0x14): Port 1 Control 4 Register 36 (0x24): Port 2 Control 4 Register 52 (0x34): Port 3 Control 4 Bit Name R/W 7-0 Default tag R/W [7:0] Note: Registers 19 and 20 (and those corresponding to ...
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Micrel, Inc. Register 25 (0x19): Port 1 Control 9 Register 41 (0x29): Port 2 Control 9 Register 57 (0x39): Port 3 Control 9 Bit Name R/W 7-0 Receive low R/W priority rate control [7:0] Register 26 (0x1A): Port 1 Control ...
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Micrel, Inc. Register 27 (0x1B): Port 1 Control 11 Register 43 (0x2B): Port 2 Control 11 Register 59 (0x3B): Port 3 Control 11 (continued Bit Name R/W 3 High priority R/W receive rate flow control enable 2 Transmit R/W differential ...
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Micrel, Inc. Register 28 (0x1C): Port 1 Control 12 Register 44 (0x2C): Port 2 Control 12 Register 60 (0x3C): Reserved, not applied to port 3 (continued) Bit Name R/W 5 Force duplex R/W 4 Advertised flow R/W control capability 3 ...
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Micrel, Inc. Register 29 (0x1D): Port 1 Control 13 Register 45 (0x2D): Port 2 Control 13 Register 61 (0x3D): Reserved, not applied to port 3 (continued) Bit Name R/W 4 Disable far end R/W fault 3 Power-down R/W 2 Disable ...
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Micrel, Inc. Register 30 (0x1E): Port 1 Status 0 Register 46 (0x2E): Port 2 Status 0 Register 62 (0x3E): Reserved, not applied to port 3 (continued) Bit Name R/W 3 Partner 100BT RO full-duplex capability 2 Partner 100BT RO half-duplex ...
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Micrel, Inc. Advanced Control Registers The IPv4 TOS priority control registers implement a fully decoded 64 bit differentiated services code point (DSCP) register used to determine priority from the 6 bit TOS field in the IP header. The most significant ...
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Micrel, Inc. Registers 104 to 109 Registers 104 to 109 define the switching engine’s MAC address. This 48-bit address is used as the SA for MAC pause control frames. Register 104 (0x68): MAC Address Register 0 Bit Name R/W 7-0 ...
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Micrel, Inc. Register 110 and 111 Use registers 110 and 111 to read or write data to the static MAC address table, VLAN table, dynamic address table, or the MIB counters. Register 110 (0x6E): Indirect Access Control 0 Bit Name ...
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Micrel, Inc. Register 117 (0x75): Indirect Data Register 3 Bit Name R/W 31-24 Indirect data R/W Register 118 (0x76): Indirect Data Register 2 Bit Name R/W 23-16 Indirect data R/W Register 119 (0x77): Indirect Data Register 1 Bit Name R/W ...
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Micrel, Inc. Bit Name 50-48 Forwarding ports 47-0 MAC address Table 12. Format of Static MAC Table (8 Entries) (continued) Examples: 1. Static Address Table Read (Read the 2 Write to reg. 110 with 0x10 (read static table selected) Write ...
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Micrel, Inc. Bit Name 19 Valid 18-16 Membership 15-12 FID 11-0 VID If 802.1Q VLAN mode is enabled, KSZ8993M will assign a VID to every ingress packet. If the packet is untagged or tagged with a null VID, the packet ...
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Micrel, Inc. Bit Name 66 MAC empty 65- valid entries 55-54 Time stamp 53-52 Source port 51-48 FID 47-0 MAC address Table 14. Format of Dynamic MAC Address Table (1K Entries) (continued) Example: Dynamic MAC Address Table Read ...
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Micrel, Inc. Port 1’s “Per Port” MIB Counters Indirect Memory Offsets are shown in the following table. Offset Counter Name 0x0 RxLoPriorityByte 0x1 RxHiPriorityByte 0x2 RxUndersizePkt 0x3 RxFragments 0x4 RxOversize 0x5 RxJabbers 0x6 RxSymbolError 0x7 RxCRCError 0x8 RxAlignmentError 0x9 RxControl8808Pkts ...
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Micrel, Inc. Offset Counter Name 0x1B TxDeferred 0x1C TxTotalCollision 0x1D TxExcessiveCollision 0x1E TxSingleCollision 0x1F TxMultipleCollision Table 17. Port 1’s “Per Port” MIB Counters Indirect Memory Offsets Bit Name 30-16 Reserved 15-0 Counter values Table 18. Format of “All Port Dropped ...
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Micrel, Inc. Then, Read reg. 117 (counter value 30-24 bit restart (reread) from this register Read reg. 118 (counter value 23-16) Read reg. 119 (counter value 15-8) Read reg. 120 (counter value 7-0) 3. MIB ...
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Micrel, Inc. Absolute Maximum Ratings Description Supply Storage Supply Voltage Input Voltage (all inputs) Output Voltage (all outputs Lead Temperature (soldering, 10 sec) Storage Temperature ( Note: 1. Exceeding the absolute maximum rating may damage the device. Stresses ...
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Micrel, Inc. Electrical Characteristics V = xx; R =xx 25°C, bold values indicate –40°C< Parameter Supply Current (including TX output driver current, KSZ8993M device only) 100BASE-TX (analog core + PLL + digital core) 100BASE-TX ...
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Micrel, Inc. Electrical Characteristics (continued) Parameter 10BaseT Receive Squelch Threshold 10BaseT Transmit (measured differentially after 1:1 transformer) VDDATX = 3.3V only Peak Differential Output Voltage Jitters Added Rise/Fall Time Note: 1. Specification for packaged product only. October 2008 (1) Symbol ...
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Micrel, Inc. Timing Specifications EEPROM Timing Figure 14. EEPROM Interface Output Timing Diagram Timing Parameter Description Clock cycle t cyc1 Setup time t s1 Hold time t h1 Output valid t ov1 October 2008 Figure 13. EEPROM Interface Input Timing ...
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Micrel, Inc. SNI Timing Timing Parameter Description Clock cycle t cyc2 Setup time t s2 Hold time t h2 Output valid t ov2 October 2008 Figure 15. SNI Input Timing Diagram Figure 16. SNI Output Timing Diagram Min Typ 100 ...
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Micrel, Inc. MII Timing MAC Mode MII Timing Figure 17. MAC-Mode MII Timing – Data Received from MII Timing Parameter Description t (100BASE-T) Clock cycle cyc3 100BASE-T tcyc3 (10BASE-T) Clock cycle 10BASE-T Setup time t s3 Hold time t h3 ...
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Micrel, Inc. PHY-Mode MII Timing Figure 19. PHY-Mode MII Timing – Data Received from MII Timing Parameter Description tcyc4 Clock cycle (100BASE-T) 100BASE-T tcyc4 (10BASE-T) Clock cycle 10BASE-T ts4 Setup time th4 Hold time tov4 Output valid October 2008 Figure ...
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Micrel, Inc. SPI Timing Input Timing Timing Parameter fC tCHSL tSLCH tCHSH tSHCH tSHSL tDVCH tCHDX tCLCH tCHCL tDLDH tDHDL October 2008 Figure 21. SPI Input Timing Description Clock frequency SPIS_N inactive hold time SPIS_N active setup time SPIS_N active ...
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Micrel, Inc. Output Timing Timing Parameter fC tCLQX tCLQV tCH tCL tQLQH tQHQL tSHQZ October 2008 Figure 22. SPI Output Timing Description Clock frequency SPIQ hold time Clock low to SPIQ valid Clock high time Clock low time SPIQ rise ...
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Micrel, Inc. Reset Timing As long as the stable supply voltages to reset high timing (minimum of10ms) are met, there is no power sequencing requirement for the KSZ8993M supply voltages (1.8V, 3.3 recommended to wait 100µsec after the ...
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Micrel, Inc. Figure 25. Recommended Circuit for Interfacing with CPU/FPGA Reset At power-on-reset and D1 provide the necessary ramp rise time to reset the Micrel device. The reset out from CPU/FPGA provides warm reset after power up. It ...
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Micrel, Inc. Selection of Isolation Transformers A 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Parameter Turns ratio Open-circuit ...
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Micrel, Inc. Package Information MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL: +1 (408) 944-0800 The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by ...