KSZ8993MI Micrel Inc, KSZ8993MI Datasheet - Page 22

• Manufacturer Part Number: KSZ8993MI
• Description: IC SWITCH 10/100 W/TXRX 128PQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8993MI

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 1.89/3.465V
• Operating Supply Voltage (min): 1.71/3.135V
• Power Dissipation: 800mW
• Supply Current: 0.1/0.19A
• Operating Temperature Classification: Industrial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-2124; KSZ8993MI

PLL Clock Synthesizer
The KSZ8993M generates 125MHz, 31.25MHz, 25MHz, and 10MHz clocks for system timing. Internal clocks are
generated from an external 25MHz crystal or oscillator.
Scrambler/De-scrambler (100BASE-TX Only)
The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline
wander. Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR).
The scrambler can generate a 2047-bit non-repetitive sequence. The receiver will then de-scramble the incoming
data stream with the same sequence at the transmitter.
100BASE-FX Operation
100BASE-FX operation is very similar to 100BASE-TX operation with the differences being that the scrambler /
de-scrambler and MLT3 encoder / decoder are bypassed on transmission and reception. In 100BASE-FX mode,
the auto negotiation feature is bypassed since there is no standard that supports fiber auto negotiation. The auto-
MDI/MDI-X feature is also disabled.
100BASE-FX Signal Detection
In fiber operation, the KSZ8993M’s FXSD1 (fiber signal detect) input pin is usually connected to the fiber
transceiver’s SD (signal detect) output pin. 100BASE-FX mode is activated when the FXSD1 input pin is greater
than 1V. When FXSD1 is between 1V and 1.8V, no fiber signal is detected and a far end fault (FEF) is generated.
When FXSD1 is over 2.2V, the fiber signal is detected.
Alternatively, the designer may choose not to implement the FEF feature. In this case, the FXSD1 input pin is tied
high to force 100BASE-FX mode.
100BASE-FX signal detection is summarized in the following table:
To ensure proper operation, a resistive voltage divider is recommended to adjust the fiber transceiver’s SD output
voltage swing to match the KSZ8993M’s FXSD1 input voltage threshold.
100BASE-FX Far End Fault
An FEF occurs when the signal detection is logically false on the receive side of the fiber transceiver. The
KSZ8993M detects a FEF when its FXSD1 input is between 1.0V and 1.8V. When an FEF occurs, the
transmission side signals the other end of the link by sending 84 1’s followed by a zero in the idle period between
frames.
Upon receiving an FEF, the LINK will go down (even when a fiber signal is detected) to indicate a fault condition.
The transmitting side is not affected when an FEF is received, and will continue to send out its normal transmit
pattern from the MAC. By default, FEF is enabled. The FEF feature can be disabled through register setting.
Micrel, Inc.
October 2008
Part Number
Less than 0.2V
Greater than 1V, but less than 1.8V
Greater than 2.2V I
Table 1. FX and TX Mode Selection
22
Mode
TX mode
FX mode
No signal detected.
Far-end fault generated
FX mode
Signal detected
M9999-020606
KSZ8993M/ML