IDT72P51369L5BB IDT, Integrated Device Technology Inc, IDT72P51369L5BB Datasheet - Page 20

• Manufacturer Part Number: IDT72P51369L5BB
• Description: IC FLOW CTRL 36BIT 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51369L5BB

• Configuration: Dual
• Density: 4.5Mb
• Access Time (max): 3.6ns
• Word Size: 36b
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 200MHz
• Supply Current: 150mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51369L5BB

AC ELECTRICAL CHARACTERISTICS
(Commercial: V
NOTES:
1. Industrial temperature range product for the 6ns is available as a standard device. All other speed grades available by special order.
2. Values guaranteed by design, not currently tested.
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
S
A
DH
C
QS
QH
CLK
CLKH
CLKL
DS
ENS
ENH
RS
RSS
RSF
RSR
OLZ (OE-
OHZ
OE
SCLK
SCKH
SCKL
SDS
SDH
SENS
SENH
SDO
SENO
SDOP
SENOP
PCSF
AS
AH
WFF
REF
STS
STH
WAF
RAE
PAF
PAE
PAELZ
(2)
(2)
Q
n)
(2)
DD
Clock Cycle Frequency (WCLK & RCLK)
Data Access Time
Clock Cycle Time
Clock High Time
Clock Low Time
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Reset Pulse Width
Reset Setup Time
Reset Output Status
Reset Recovery Time
Output Enable to Output in Low-Impedance
Output Enable to Output in High-Impedance
Output Enable to Data Output Ready
Clock Cycle Frequency (SCLK)
Serial Clock Cycle
Serial Clock High
Serial Clock Low
Serial Data In Setup
Serial Data In Hold
Serial Enable Setup
Serial Enable Hold
SCLK to Serial Data Out
SCLK to Serial Enable Out
Serial Data Out Propagation Delay
Serial Enable Propagation Delay
Programming Complete to Status Flag
Address Setup
Address Hold
Write Clock to Full Flag
Read Clock to Empty Flag
PAE/PAF Strobe Setup
PAE/PAF Strobe Hold
Queue Setup
Queue Hold
WCLK to PAF flag
RCLK to PAE flag
Write Clock to Synchronous Almost-Full Flag Bus
Read Clock to Synchronous Almost-Empty Flag Bus
RCLK to PAE Flag Bus to Low-Impedance
= 1.8V ± 0.10V, T
A
= 0°C to +70°C;Industrial: V
Parameter
DD
= 1.8V ± 0.10V, T
20
Min.
2.25
2.25
100
IDT72P51339L5
IDT72P51349L5
IDT72P51359L5
IDT72P51369L5
0.6
1.5
0.5
1.5
0.5
0.6
0.6
0.6
1.2
1.2
0.6
0.6
1.5
0.5
1.5
0.5
1.5
0.5
0.6
0.6
0.6
0.6
0.6
—
30
15
—
10
—
45
45
20
20
—
—
—
—
—
5
Commercial
A
= -40°C to +85°C; JEDEC JESD8-A compliant)
7+1 SCLK
Max.
200
3.6
3.6
3.6
3.6
3.7
3.7
3.6
3.6
3.6
3.6
3.6
3.6
3.6
—
—
—
—
—
—
—
—
—
10
—
10
—
—
—
—
—
—
—
20
20
—
—
—
—
—
—
Min.
100
0.6
2.7
2.7
2.0
0.5
2.0
0.5
0.6
0.6
0.6
1.2
1.2
0.6
0.6
2.0
0.5
1.5
0.5
2.0
0.5
0.6
0.6
0.6
0.6
0.6
—
30
15
—
10
—
45
45
20
20
—
—
—
—
—
IDT72P51339L6
IDT72P51349L6
IDT72P51359L6
IDT72P51369L6
6
Com'l & Ind'l
COMMERCIAL AND INDUSTRIAL
7+1 SCLK
Max.
166
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
—
—
—
—
—
—
—
—
—
10
—
10
—
—
—
—
—
—
—
20
20
—
—
—
—
—
—
(1)
TEMPERATURE RANGES
clock cycles
AUGUST 4, 2005
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns