IDT72P51369L5BB IDT, Integrated Device Technology Inc, IDT72P51369L5BB Datasheet - Page 27

• Manufacturer Part Number: IDT72P51369L5BB
• Description: IC FLOW CTRL 36BIT 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51369L5BB

• Configuration: Dual
• Density: 4.5Mb
• Access Time (max): 3.6ns
• Word Size: 36b
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 200MHz
• Supply Current: 150mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51369L5BB

TABLE 5 — READ ADDRESS BUS, RDADD[7:0]
READ QUEUE SELECTION AND READ OPERATION
(STANDARD MODE)
trol devices can be configured up to a maximum of 8 queues which data can
be read via a common read port using the data outputs (Qout), read clock
(RCLK) and read enable (REN). An output enable, OE control pin is also
provided to allow High-Impedance selection of the Qout data outputs. The multi-
queue device read port operates in standard IDT mode and “First Word Fall
Through” mode (see Figure 46, Write Operations in First Word Fall Through).
The queue to be read is selected by the address presented on the read address
bus (RDADD) during a rising edge on RCLK while read address enable
(RADEN) is HIGH. The state of REN does not impact the queue selection. The
queue selection requires 4 RCLK cycles. All subsequent data reads will be from
this queue until another queue is selected.
device. The read port is designed such that 100% bus utilization can be
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
The IDT72P51339/72P51349/72P51359/72P51369 multi-queue flow-con-
Standard mode operation is defined as individual words will be read from the
Read Queue
PAEn/PRn
Quadrant
Operation RCLK
Select
Select
RADEN
1
0
Status Word
Address
0000
27
ESTR
0
1
obtained. This means that data can be read out of the device on every RCLK
rising edge including the cycle that a new queue is being addressed.
(see Figure 48, Read Queue Select, Read Operation). RADEN goes high
signaling a change of queue (clock cycle “D”). The address on RDADD at that
time determines the next queue. Data presented during that cycle will be
read.Reading data can continue from the active, provided REN is LOW. If REN
is HIGH (inactive) for these two clock cycles, data will not be read from the queue.
If a new selected queue is empty, any reads from that queue will be prevented.
Data cannot be read from an empty queue. Remember that OE allows the user
to place the data output bus (Qout) into High-Impedance and the data can be
read in to the output register regardless of OE.
13, 15, and 16 for read queue selection and read port operation timing diagrams.
Changing queues requires a minimum of four RCLK cycles on the read port
Refer to Table 5, for Read Address Bus arrangement. Also, refer to Figures
Queue Status on PAEn/PRn Bus
Q0 : Q7 → PAF0 : PAF7
Device Select
(Compared to
ID2,1,0)
Device Select
(Compared to
ID2,1,0)
7 6 5
7 6 5
RDADD[7:0]
Read Queue Address
(2 bits = 4 Queues
3 bits = 8 Queues)
X
4 3
4
3 2 1 0
Status Word
Address
2 1 0
COMMERCIAL AND INDUSTRIAL
6716 drw12
TEMPERATURE RANGES
AUGUST 4, 2005