IDT72P51369L5BB IDT, Integrated Device Technology Inc, IDT72P51369L5BB Datasheet - Page 23

• Manufacturer Part Number: IDT72P51369L5BB
• Description: IC FLOW CTRL 36BIT 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51369L5BB

• Configuration: Dual
• Density: 4.5Mb
• Access Time (max): 3.6ns
• Word Size: 36b
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 200MHz
• Supply Current: 150mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51369L5BB

SERIAL PROGRAMMING
ing the user with flexibility in how queues are configured in terms of the number
of queues, depth of each queue and position of the PAF/PAE flags within
respective queues. All user programming is done via the serial port after a master
reset has taken place. Internally the multi-queue device has setup registers
which must be serially loaded, these registers contain values for every queue
within the device, such as the depth and PAE/PAF offset values. The
IDT72P51339/72P51349/72P51359/72P51369 devices are capable of up to
8 queues and therefore contain 128 sets of registers for the setup of each queue.
will require serial programming by the user. It is recommended that the user
utilize a ‘C’ program provided by IDT, this program will prompt the user for all
information regarding the multi-queue setup. The program will then generate
a serial bit stream which should be serially loaded into the device via the serial
port. For the IDT72P51339/72P51349/72P51359/72P51369 devices the
serial programming requires a total number of serially loaded bits per device,
(SCLK cycles with SENI enabled), calculated by: 19+(Qx72) where Q is the
number of queues the user wishes to setup within the device.
serially loaded. Data present on the SI (serial in), input is loaded into the serial
port on a rising edge of SCLK (serial clock), provided that SENI (serial in
enable), is LOW. Once serial programming of the device has been successfully
completed the device will indicate this via the SENO (serial output enable) going
active, LOW. Upon detection of completion of programming, the user should
cease all programming and take SENI inactive, HIGH. Note, SENO follows SENI
once programming of a device is complete. Therefore, SENO will go LOW after
programming provided SENI is LOW, once SENI is taken HIGH again, SENO
will also go HIGH. The operation of the SO output is similar, when programming
of a given device is complete, the SO output will follow the SI input.
should be cascaded. The user can load all devices via the serial input port control
pins, SI & SENI, of the first device in the chain. Again, the user may utilize the
‘C’ program to generate the serial bit stream, the program prompting the user
for the number of devices to be programmed. The SENO and SO (serial out)
of the first device should be connected to the SENI and SI inputs of the second
device respectively and so on, with the SENO & SO outputs connecting to the
SENI & SI inputs of all devices through the chain. All devices in the chain should
be connected to a common SCLK. The serial output port of the final device should
be monitored by the user. When SENO of the final device goes LOW, this
indicates that serial programming of all devices has been successfully com-
pleted. Upon detection of completion of programming, the user should cease all
programming and take SENI of the first device in the chain inactive, HIGH.
by the user, this is the first device to have its internal registers serially loaded
by the serial bit stream. When programming of this device is complete it will take
its SENO output LOW and bypass the serial data loaded on the SI input to its
SO output. The serial input of the second device in the chain is now loaded with
the data from the SO of the first device, while the second device has its SENI
input LOW. This process continues through the chain until all devices are
programmed and the SENO of the final device (or master device, ID = '000')
goes LOW.
operations, (queue selections on the read and write ports) may begin. When
connected in expansion configuration, the IDT72P51339/72P51349/72P51359/
72P51369 devices require a total number of serially loaded bits per device to
complete serial programming, (SCLK cycles with SENI enabled), calculated by:
n[19+(Qx72)] where Q is the number of queues the user wishes to setup within
the device, where n is the number of devices in the chain.
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
The multi-queue flow-control device is a fully programmable device, provid-
During a Master Reset if the DFM (Default Mode) input is LOW, then the device
Once the master reset is complete and MRS is HIGH, the device can be
If devices are being used in expansion configuration the serial ports of devices
As mentioned, the first device in the chain has its serial input port controlled
Once all serial programming has been successfully completed, normal
23
for connection and timing information.
DEFAULT PROGRAMMING
queue device will be configured for default programming, (serial programming
is not permitted). Default programming provides the user with a simpler,
however limited means to setup the multi-queue flow-control device, rather than
using the serial programming method. The default mode will configure a multi-
queue device with the maximum number of queues setup, and the available
memory allocated equally between the queues. The values of the PAE/PAF
offsets is determined by the state of the DF (default) pin during a master reset.
mode will setup 8 queues, each queue being 512 x 36, 1024 x 36, 2048 x36,
and 4096 x 36 deep respectively. For each device, the value of the PAE/PAF
offsets is determined at master reset by the state of the DF input. If DF is LOW
then both the PAE & PAF offset will be 8, if HIGH then the value is 128.
vices in default mode the user simply has to apply WCLK cycles after a master
reset, until SENO goes LOW, this signals that default programming is complete.
These clock cycles are required for the device to load its internal setup registers.
When a single multi-queue device is used, the completion of device program-
ming is signaled by the SENO output of a device going from HIGH to LOW. Note,
that SENI must be held LOW when a device is setup for default programming
mode.
SENI of the first device in a chain can be held LOW. The SENO of a device should
connect to the SENI of the next device in the chain. The SENO of the final device
is used to indicate that default programming of all devices is complete. When the
master (ID='000') SENO goes LOW normal operations may begin. Again, all
devices will be programmed with their maximum number of queues and the
memory divided equally between them. Please refer to Figure 38, Default
Programming.
PARALLEL PROGRAMMING
LOW then LOW to HIGH) if the DFM (Default Mode) input signal is HIGH and
the QSEL 1 input signal is LOW the Multi-Queue Flow Control device is
configured for Parallel Programming. Parallel Programming enables the
number of queues within the device to be set through either the Write Address
(WRADD) bus or Read Address (RDADD) bus after the Master Reset cycle.
Within Parallel Programming mode the Multi-Queue (MQ) device program-
mable parameters are; number of queues, queue depth, PAE/PAF flag offset
value, bus matching and the I/O voltage level. As previously indicated, the
number of queues are configured using the write or read address bus,
however bus matching is set during the Master Reset cycle. The value that is
set during the Master Reset cycle is determined by the Bus Matching (BM) bits.
For the IDT72P51339/72P51349/72P51359/72P51369 devices in Parallel
Programming Mode the value of the PAE/PAF offsets at master reset is
determined by the state of the DF input. If DF is LOW then both the PAE & PAF
offset will be 8, if HIGH then the value is 128.
devices in Parallel Programming Mode the user simply has to apply WCLK
cycles after a master reset, untilSENO goes LOW, this signals that Parallel
Programming is complete. These clock cycles are required for the device to
load its internal setup registers. When a single multi-queue device is used, the
completion of device programming is signaled by the SENO output of a device
going from HIGH to LOW. Note, that SENI must be held LOW when a device
is setup for Parallel Programming mode.
See Figure 42, Serial Port Connection and Figure 43, Serial Programming
During a Master Reset if the DFM (Default Mode) input is HIGH the multi-
For the IDT72P51339/72P51349/72P51359/72P51369 devices the default
When configuring the IDT72P51339/72P51349/72P51359/72P51369 de-
When multi-queue devices are connected in expansion configuration, the
During a Master Reset cycle (i.e. the MRS signal transitions from HIGH to
When configuring the IDT72P51339/72P51349/72P51359/72P51369
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AUGUST 4, 2005