IDT72P51369L5BB IDT, Integrated Device Technology Inc, IDT72P51369L5BB Datasheet - Page 47

• Manufacturer Part Number: IDT72P51369L5BB
• Description: IC FLOW CTRL 36BIT 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51369L5BB

• Configuration: Dual
• Density: 4.5Mb
• Access Time (max): 3.6ns
• Word Size: 36b
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 200MHz
• Supply Current: 150mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51369L5BB

address the third status word, Queue[16:23], the RDADD address is “xxxx0010”.
PAE[0:7] gets status of queues, Queue[16:23] respectively. To address the
fourth status word, Queue[24:31], the RDADD address is “xxxx0011”.
PAE[0:1] gets status of queues, Queue[24:25] respectively. Remember, only
26 queues were setup, so when status word 4 is selected the unused outputs
PAE[2:7] will be don't care states.
queue ‘x’ on the same cycle as a status word switch which will include the queue
‘x’, then there may be an extra RCLK cycle delay before that queues status is
correctly shown on the respective output of the PAEn/PRn bus.
word on the PAEn/PRn bus can change every RCLK cycle. Also, data can be
read out of a Queue on the same RCLK rising edge that a status word is being
selected, the only restriction being that a read queue selection and PAEn/PRn
status word selection cannot be made on the same RCLK cycle.
status output on PAE[0:7] constantly.
device the PAEn/PRn busses of all devices are connected together, when
switching between status words of different devices the user must utilize the 3
most significant bits of the RDADD address bus (as well as the 2 LSB’s). These
3 MSb’s correspond to the device ID inputs, which are the static inputs, ID0, ID1
& ID2.
for timing information. Also refer to Table 5, Read Address Bus, RDADD.
PAEn – POLLED BUS
(looped) mode. In polled mode the PAEn/PRn bus automatically cycles through
the 4 status words within the device regardless of how many queues have been
setup in the part. Every rising edge of the RCLK causes the next status word
to be loaded on the PAEn/PRn bus. The device configured as the master (MAST
input tied HIGH), will take control of the PAEn/PRn after MRS goes LOW. For
the whole RCLK cycle that the first status word is on PAEn/PRn the ESYNC
(PAEn/PRn bus sync) output will be HIGH, for all other status words, this ESYNC
output will be LOW. This ESYNC output provides the user with a mark with which
they can synchronize to the PAEn/PRn bus, ESYNC is always HIGH for the
RCLK cycle that the first status word of a device is present on the PAEn/PRn
bus.
will be set as the Master (ID='000'), MAST input tied HIGH, all other devices
will have MAST tied LOW. The master device is the first device to take control
of the PAEn/PRn bus and will place its first status word on the bus on the rising
edge of RCLK after the MRS input goes LOW. For the next n RCLK cycles
(n=number of queues divided by 8 with n incrementing by one should there be
a remainder) the master device will maintain control of the PAEn/PRn bus and
cycle its status words through it, all other devices hold their PAEn/PRn outputs
in High-Impedance. When the master device has cycled all of its status words
it passes a token to the next device in the chain and that device assumes control
of the PAEn/PRn bus and then cycles its status words and so on, the PAEn/PRn
bus control token being passed on from device to device. This token passing
is done via the EXO outputs and EXI inputs of the devices (“PAE Expansion Out”
and “PAE Expansion In”). The EXO output of the master device connects to the
EXI of the second device in the chain and the EXO of the second connects to
the EXI of the third and so on. The final device in a chain has its EXO connected
to the EXI of the first device, so that once the PAEn/PRn bus has cycled through
all status words of all devices, control of the PAEn/PRn will pass to the master
device again and so on. The ESYNC of each respective device will operate
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
Note, that if a read or write operation is occurring to a specific queue, say
Status words can be selected on consecutive clock cycles, that is the status
If 8 or less queues are setup then queues, Queue[0:7] have their PAE/PR
When the multi-queue devices are connected in expansion of more than one
Please refer to Figure 62, PAE n/ PR n - Direct Mode Status Word Selection
If FM is HIGH at master reset then the PAEn/PRn bus operates in Polled
When devices are connected in expansion configuration, only one device
47
independently and simply indicate when that respective device has taken control
of the bus and is placing its first status word on to the PAEn/PRn bus.
the EXO output of the same device. In single device mode a token is still required
to be passed into the device for accessing the PAEn bus.
PACKET READY FLAG
Ready feature. During a Master Reset Packet Mode is selected by PKT = HIGH.
The PR discrete flag, provides a packet ready status of the active queue selected
on the read port. A packet ready status is individually maintained on all queues;
however only the queue selected on the read port has its packet ready status
indicated on the PR output flag. A packet is available on the output for reading
when both PR and OR are asserted LOW. If less than a full packet is available,
the PR flag will be HIGH (packet not ready). In packet mode, no words can be
read from a queue until a complete packet has been written into that queue,
regardless of REN.
becomes the Packet Ready bus, PRn. When configured in Direct Bus (FM =
LOW during a master reset), the PRn bus provides packet ready status in 8
queue increments. The PRn bus supports either Polled or Direct modes of
operation. The PRn mode of operation is configured through the Flag Mode
(FM) bit during a Master Reset.
significant bits of the 36-bit data bus are used as “packet markers”. On the write
port these are bits D34 (Transmit Start of Packet,) D35 (Transmit End of Packet)
and on the read port Q34, Q35. All four bits are monitored by the packet control
logic as data is written into and read out from the queues. The packet ready status
for individual queues is then determined by the packet ready logic.
selected queue as the “Transmit Start of Packet”, TSOP. To further clarify, when
the user requires a word being written to be marked as the start of a packet, the
TSOP input (D34) must be HIGH for the same WCLK rising edge as the word
that is written. The TSOP marker is stored in the queue along with the data it was
written in until the word is read out of the queue via the read port.
being written into the selected queue as the “Transmit End of Packet” TEOP.
When the user requires a word being written to be marked as the end of a packet,
the TEOP input must be HIGH for the same WCLK rising edge as the word that
is written in. The TEOP marker is stored in the queue along with the data it was
written in until the word is read out of the queue via the read port.
they enter respective queues via the write port and as they exit queues via the
read port. The multi-queue internal logic increments and decrements a packet
counter, which is provided for each queue. The functionality of the packet ready
logic provides status as to whether at least one full packet of data is available
within the selected queue. A partial packet in a queue is regarded as a packet
not ready and PR (active LOW) will be HIGH. In Packet mode, no words can
be read from a queue until at least one complete packet has been written into
the queue, regardless of REN. For example, if a TSOP has been written and
some number of words later a TEOP is written a full packet of data is deemed
to be available, and the PR flag and OR will go active LOW. Consequently if reads
begin from a queue that has only one complete packet and the RSOP is detected
on the output port as data is being read out, PR will go inactive HIGH. OR will
remain LOW indicating there is still valid data being read out of that queue until
the REOP is read. The user may proceed with the reading operation until the
current packet has been read out and no further complete packets are available.
If during that time another complete packet has been written into the queue and
The 36-bit multi-queue flow-control device provides the user with a Packet
When packet mode is selected the Programmable Almost Empty bus, PAEn,
When the multi-queue is configured for packet mode operation, the two most
On the write port D34 is used to “mark” the first word being written into the
The packet ready logic monitors all start and end of packet markers both as
When operating in single device mode the EXI input must be connected to
On the write port D35 is used to “mark” the last word of the packet currently
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AUGUST 4, 2005