SI5322/23-EVB Silicon Laboratories Inc, SI5322/23-EVB Datasheet - Page 12

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SI5322/23-EVB

Manufacturer Part Number
SI5322/23-EVB
Description
BOARD EVAL FOR SI5322/23
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of SI5322/23-EVB

Main Purpose
Timing, Clock Generator
Utilized Ic / Part
SI5322, SI5323
Processor To Be Evaluated
Si5322 and Si5323
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Si5322
4. Package Outline: 36-Pin QFN
Figure 3 illustrates the package details for the Si5322. Table 4 lists the values for the dimensions shown in the
illustration.
12
Notes:
Symbol
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VJJD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body
A1
D2
E2
D
A
b
e
E
Components.
0.80
0.00
0.18
3.95
3.95
Min
Millimeters
6.00 BSC
0.50 BSC
6.00 BSC
Nom
0.85
0.02
0.25
4.10
4.10
Figure 3. 36-Pin Quad Flat No-lead (QFN)
Table 4. Package Dimensions
Max
0.90
0.05
0.30
4.25
4.25
Preliminary Rev. 0.5
Symbol
aaa
bbb
ddd
eee
ccc
L
θ
0.50
Min
Millimeters
Nom
0.60
Max
0.70
0.10
0.10
0.08
0.10
0.05
12º

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