SI5322/23-EVB Silicon Laboratories Inc, SI5322/23-EVB Datasheet - Page 2

• Manufacturer Part Number: SI5322/23-EVB
• Description: BOARD EVAL FOR SI5322/23
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5322/23-EVB

• Main Purpose: Timing, Clock Generator
• Utilized Ic / Part: SI5322, SI5323
• Processor To Be Evaluated: Si5322 and Si5323
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si5322
Table 1. Performance Specifications
(V
2
Temperature Range
Supply Voltage
Supply Current
Input Clock Frequency
(CKIN1, CKIN2)
Output Clock Frequency
(CKOUT1, CKOUT2)
3-Level Input Pins
Input Mid Current
Input Clocks (CKIN1, CKIN2)
Differential Voltage
Swing
Common Mode
Voltage
Rise/Fall Time
Duty Cycle
(Minimum Pulse Width)
Output Clocks (CKOUT1, CKOUT2)
Common Mode
Differential Output
Swing
Single Ended Output
Swing
Rise/Fall Time
Notes:
DD
1. For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision
2. This is the amount of leakage that the 3 level input can tolerate from an external driver. See the Family Reference
= 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T
Clock Family Reference Manual. This document can be downloaded from
Documentation)
Manual. In most designs, an external resistor voltage divider is recommended.
Parameter
.
CKN
CKN
CKO
Symbol
CKN
CKN
CK
V
CK
I
V
V
V
I
IMM
OCM
T
DD
DD
OD
SE
A
OF
VCM
DPP
TRF
TRF
F
DC
cation ratio pin-selectable from table
www.silabs.com/timing
Laboratories configuration software
Clock Family Reference Manual at
Input frequency and clock multipli-
FRQTBL settings. Consult Silicon
DSPLLsim or Any-Rate Precision
A
mentation) for table selections.
of values using FRQSEL and
= –40 to 85 ºC)
1
Both CKOUTs enabled
Both CKOUTs enabled
LVPECL format output
Whichever is smaller
CMOS format output
Tristate/Sleep Mode
f
CKOUT2 disabled
CKOUT2 disabled
OUT
f
Preliminary Rev. 0.5
OUT
Test Condition
See Note 2.
2.5 V ±10%
3.3 V ±10%
100 Ω load
1.8 V ±5%
line-to-line
= 622.08 MHz
20–80%
LVPECL
20–80%
= 19.44 MHz
(click on Docu-
www.silabs.com/timing
V
DD
19.44
19.44
2.97
2.25
1.71
0.25
Min
–40
0.9
1.0
1.1
1.1
0.5
–2
40
—
—
—
—
—
—
—
– 1.42
2
Typ
251
217
204
194
165
230
3.3
2.5
1.8
25
—
—
—
—
—
—
—
—
—
—
—
—
—
V
(click on
1049.76
DD
707.35
Max
3.63
2.75
1.89
TBD
1.95
0.93
279
243
234
220
350
1.9
1.4
1.7
1.9
85
11
60
—
– 1.25
2
MHz
MHz
Unit
V
mA
mA
mA
mA
mA
µA
ºC
ns
ns
ps
%
V
V
V
V
V
V
V
V
V
PP