SI5322/23-EVB Silicon Laboratories Inc, SI5322/23-EVB Datasheet - Page 3

• Manufacturer Part Number: SI5322/23-EVB
• Description: BOARD EVAL FOR SI5322/23
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5322/23-EVB

• Main Purpose: Timing, Clock Generator
• Utilized Ic / Part: SI5322, SI5323
• Processor To Be Evaluated: Si5322 and Si5323
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 1. Performance Specifications
(V
Table 2. Absolute Maximum Ratings
Duty Cycle Uncertainty
PLL Performance
Jitter Generation
Jitter Transfer
Phase Noise
Subharmonic Noise
Spurious Noise
Package
Thermal Resistance
Junction to Ambient
Notes:
DC Supply Voltage
LVCMOS Input Voltage
Operating Junction Temperature
Storage Temperature Range
ESD HBM Tolerance (100 pF, 1.5 kΩ); All pins except CKIN+/CKIN–
ESD MM Tolerance; All pins except CKIN+/CKIN–
ESD HBM Tolerance (100 pF, 1.5 kΩ); CKIN+/CKIN–
ESD MM Tolerance; CKIN+/CKIN–
Latch-Up Tolerance
Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
DD
1. For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision
2. This is the amount of leakage that the 3 level input can tolerate from an external driver. See the Family Reference
= 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T
Clock Family Reference Manual. This document can be downloaded from
Documentation)
Manual. In most designs, an external resistor voltage divider is recommended.
restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods of time may affect device reliability.
Parameter
.
Symbol
SP
SP
CKO
CKO
Parameter
J
J
θ
GEN
SUBH
SPUR
PK
JA
DC
PN
A
Phase Noise @ 100 kHz Offset
Differential 100 Ω Line-to-Line
= –40 to 85 ºC)
1
(n > 1, n x F3 < 100 MHz)
(Continued)
Measured at 50% point
LVPECL output format
f
Max spur @ n x F3
OUT
fo = 622.08 MHz,
Preliminary Rev. 0.5
50 kHz–80 MHz
12 kHz–20 MHz
Test Condition
100 kHz offset
100 Hz offset
10 kHz offset
1 MHz offset
1 kHz offset
= 622.08 MHz
LVPECL
Still Air
Symbol
T
V
T
V
STG
JCT
DIG
www.silabs.com/timing
DD
Min
–40
—
—
—
—
—
—
—
—
—
—
—
–0.3 to (V
–0.5 to 3.6
–55 to 150
–55 to 150
JESD78 Compliant
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0.05
Value
Typ
0.6
0.6
38
—
200
700
150
2
DD
(click on
+ 0.3)
Max
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0.1
Si5322
40
—
Unit
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
kV
ps rms
ºC
ºC
ps rms
V
V
V
V
V
ºC/W
Unit
dBc
dBc
dB
ps
3