SI5322/23-EVB Silicon Laboratories Inc, SI5322/23-EVB Datasheet - Page 9

• Manufacturer Part Number: SI5322/23-EVB
• Description: BOARD EVAL FOR SI5322/23
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5322/23-EVB

• Main Purpose: Timing, Clock Generator
• Utilized Ic / Part: SI5322, SI5323
• Processor To Be Evaluated: Si5322 and Si5323
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Pin #
21
23
22
27
26
25
24
Pin Name
FRQSEL3
FRQSEL2
FRQSEL1
FRQSEL0
BWSEL1
BWSEL0
CS_CA
Table 3. Si5322 Pin Descriptions (Continued)
I/O
I/O
I
I
Signal Level
LVCMOS
3-Level
3-Level
Preliminary Rev. 0.5
Input Clock Select/Active Clock Indicator.
Input: If manual clock selection mode is chosen
Output: If automatic clock selection mode is chosen
Bandwidth Select.
Three level inputs that select the DSPLL closed loop band-
width. Detailed operations and timing characteristics for
these pins may be found in the Any-Rate Precision Clock
Family Reference Manual.
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
Multiplier Select.
Three level inputs that select the input clock and clock multi-
plication ratio, depending on the FRQTBL setting. Consult
the Any-Rate Precision Clock Family Reference Manual or
DSPLLsim configuration software for settings, both avail-
able for download at
mentation).
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
(AUTOSEL = L), this pin functions as the manual
input clock selector. This input is internally deglitched
to prevent inadvertent clock switching during
changes in the CS input state.
0 = Select CKIN1.
1 = Select CKIN2.
If configured as input, must be set high or low.
(AUTOSEL = M or H), this pin indicates which of
the two input clocks is currently the active clock. If
alarms exist on both CKIN1 and CKIN2, indicating
that the digital hold state has been entered, CA will
indicate the last active clock that was used before
entering the hold state.
0 = CKIN1 active input clock.
1 = CKIN2 active input clock.
www.silabs.com/timing
Description
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Si5322
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