SI5322/23-EVB Silicon Laboratories Inc, SI5322/23-EVB Datasheet - Page 6

• Manufacturer Part Number: SI5322/23-EVB
• Description: BOARD EVAL FOR SI5322/23
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5322/23-EVB

• Main Purpose: Timing, Clock Generator
• Utilized Ic / Part: SI5322, SI5323
• Processor To Be Evaluated: Si5322 and Si5323
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si5322
1. Functional Description
The Si5322 is a low jitter, precision clock multiplier for
high-speed communication systems, including SONET
OC-48/OC-192, SDH STM-16/64 Ethernet, and Fibre
Channel. The Si5322 accepts dual clock inputs ranging
from 19.44 to 707 MHz and generates two frequency-
multiplied clock outputs ranging from 19.44 to 1050
MHz. The two input clocks are at the same frequency
and the two output clocks are at the same frequency.
The input clock frequency and clock multiplication ratio
are selectable from a table of popular SONET, Ethernet,
and Fibre Channel rates. In addition to providing clock
multiplication in SONET and datacom applications, the
Si5322
translations. Silicon Laboratories offers a PC-based
software utility, DSPLLsim, that can be used to look up
valid Si5322 frequency translations. This utility can be
downloaded from
Documentation).
The Si5322 is recommended for applications in which
the input clock is relatively low jitter and only clock
multiplication is required. The Si5322 is based on
Silicon
technology,
synthesis in a highly integrated PLL solution that
eliminates the need for external VCXO and loop filter
components. The Si5322 PLL loop bandwidth is
selectable via the BWSEL[1:0] pins and supports a
range from 30 kHz to 1.5 MHz. The DSPLLsim software
utility can be used to calculate valid loop bandwidth
settings for a given input clock frequency/clock
multiplication ratio. The Si5322 monitors all input clocks
for loss of signal and provides a LOS alarm when it
detects a missing clock.
In the case when the input clocks enter alarm
conditions, the PLL will freeze the DCO output
frequency near its last value to maintain operation with
an internal state close to the last valid operating state.
The Si5322 has two differential clock outputs. The
electrical format of the clock outputs is programmable to
support LVPECL, LVDS, CML, or CMOS loads. If not
required, the second clock output can be powered down
to minimize power consumption. For system-level
debugging, a bypass mode is available which drives the
output clock directly from the input clock, bypassing the
internal DSPLL. The device is powered by a single 1.8,
2.5, or 3.3 V supply.
6
supports
Laboratories'
which
http://www.silabs.com/timing
SONET-to-datacom
provides
3rd-generation
any-rate
frequency
frequency
(click on
DSPLL
Preliminary Rev. 0.5
®
1.1. Further Documentation
Consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual (FRM) for detailed
information about the Si5322. Additional design support
is available from Silicon Laboratories through your
distributor.
Silicon Laboratories has developed a PC-based
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. The FRM and this utility can be
downloaded from http://www.silabs.com/timing; click on
Documentation.