EVAL-AD7679CBZ Analog Devices Inc, EVAL-AD7679CBZ Datasheet - Page 24

• Manufacturer Part Number: EVAL-AD7679CBZ
• Description: BOARD EVALUATION FOR AD7679
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7679CBZ

• Number Of Adc's: 1
• Number Of Bits: 18
• Sampling Rate (per Second): 570k
• Data Interface: Serial, Parallel
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 89mW @ 500kSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7679
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7679
External Clock Data Read during Conversion
Figure 41 shows the detailed timing diagrams of this method.
During a conversion, while both CS and RD are low, the result
of the previous conversion can be read. The data is shifted out
MSB first with 18 clock pulses, and is valid on both the rising
and falling edge of the clock. The 18 bits have to be read before
the current conversion is complete. If that is not done,
RDERROR is pulsed high and can be used to interrupt the host
interface to prevent incomplete data reading. There is no daisy-
chain feature in this mode, and the RDC/SDIN input should
always be tied either high or low.
To reduce performance degradation due to digital activity, a fast
discontinuous clock is recommended to ensure that all bits are
read during the first half of the conversion phase. It is also
possible to begin to read the data after conversion and continue
to read the last bits even after a new conversion has been
initiated.
CNVST IN
SCLK IN
CS IN
RDC/SDIN
Figure 42. Two AD7679s in a Daisy-Chain Configuration
#2 (UPSTREAM)
AD7679
BUSY
SDOUT
CNVST
SCLK
CS
RDC/SDIN
#1 (DOWNSTREAM)
AD7679
BUSY
SDOUT
CNVST
SCLK
CS
03085-0-044
BUSY
OUT
DATA
OUT
Rev. A | Page 24 of 28
MICROPROCESSOR INTERFACING
The AD7679 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and for ac signal
processing applications interfacing to a digital signal processor.
The AD7679 is designed to interface either with a parallel 8-bit
or 16-bit wide interface, or with a general-purpose serial port or
I/O ports on a microcontroller. A variety of external buffers can
be used with the AD7679 to prevent digital noise from coupling
into the ADC. The following section illustrates the use of the
AD7679 with an SPI equipped DSP, the ADSP-219x.
SPI Interface (ADSP-219x)
Figure 43 shows an interface diagram between the AD7679 and
the SPI equipped ADSP-219x. To accommodate the slower
speed of the DSP, the AD7679 acts as a slave device, and data
must be read after conversion. This mode also allows the daisy-
chain feature. The convert command could be initiated in
response to an internal timer interrupt. The 18-bit output data
are read with 3-byte SPI access. The reading process could be
initiated in response to the end-of-conversion signal (BUSY
going low) using an interrupt line of the DSP. The serial
interface (SPI) on the ADSP-219x is configured for master
mode (MSTR) = 1, Clock Polarity Bit (CPOL) = 0, Clock Phase
Bit (CPHA) = 1, and SPI interrupt enable (TIMOD) = 00, by
writing to the SPI Control register (SPICLTx). It should be
noted that to meet all timing requirements, the SPI clock should
be limited to 17 Mbits/s, which allow it to read an ADC result in
about 1.1 μs. When a higher sampling rate is desired, use of one
of the parallel interface modes is recommended.
DVDD
SER/PAR
EXT/INT
RD
INVSCLK
Figure 43. Interfacing the AD7679 to an SPI Interface
AD7679*
* ADDITIONAL PINS OMITTED FOR CLARITY
SDOUT
CNVST
BUSY
SCLK
CS
PFx
SPIxSEL (PFx)
MISOx
SCKx
PFx or TFSx
ADSP-219x*
03085-0-045