CDB5534U Cirrus Logic Inc, CDB5534U Datasheet - Page 12

• Manufacturer Part Number: CDB5534U
• Description: EVAL BOARD FOR CS5534
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5534U

• Number Of Adc's: 1
• Number Of Bits: 24
• Sampling Rate (per Second): 3.84k
• Data Interface: Serial
• Inputs Per Adc: 2 Single
• Input Range: 0 ~ 2.5 V
• Power (typ) @ Conditions: 35mW @ 5 V
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS5534
• Description/function: Audio DSPs
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• For Use With/related Products: C8051F320
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1016

2. GENERAL DESCRIPTION
The CS5531/32/33/34 are highly integrated ∆Σ An-
alog-to-Digital Converters (ADCs) which use
charge-balance techniques to achieve 16-bit
(CS5531/33) and 24-bit (CS5532/34) performance.
The ADCs are optimized for measuring low-level
unipolar or bipolar signals in weigh scale, process
control, scientific, and medical applications.
To accommodate these applications, the ADCs
come as either two-channel (CS5531/32) or four-
channel (CS5533/34) devices and include a very-
low-noise, chopper-stabilized, programmable-gain
instrumentation amplifier (PGIA, 6 nV/√Hz @ 0.1
Hz) with selectable gains of 1×, 2×, 4×, 8×, 16×,
32×, and 64×. These ADCs also include a fourth or-
der ∆Σ modulator followed by a digital filter which
provides twenty selectable output word rates of 6.25,
7.5, 12.5, 15, 25, 30, 50, 60, 100, 120, 200, 240, 400,
480, 800, 960, 1600, 1920, 3200, and 3840 Samples
per second (MCLK = 4.9152 MHz).
To ease communication between the ADCs and a
microcontroller, the converters include a simple
three-wire serial interface which is SPI and Mi-
12
AIN4+
AIN1+
AIN2+
AIN1+
AIN4-
AIN1-
AIN2-
AIN1-
*
*
*
CS5531/32 IN+
CS5533/34
M
U
M
U
X
X
IN-
IN+
IN-
IN+
IN-
GAIN is the gain setting of the PGIA (i.e. 2, 4, 8, 16, 32, 64)
Figure 3. Multiplexer Configuration
XGAIN
X1
X1
1000 Ω
1000 Ω
22 nF
X 1
X 1
C1 PIN
C2 PIN
crowire compatible with a Schmitt-trigger input on
the serial clock (SCLK).
2.1. Analog Input
Figure 3 illustrates a block diagram of the
CS5531/32/33/34. The front end consists of a multi-
plexer, a unity gain coarse/fine charge input buffer,
and a programmable gain chopper-stabilized instru-
mentation amplifier. The unity gain buffer is activat-
ed any time conversions are performed with a gain
of one and the instrumentation amplifier is activated
any time conversions are performed with gain set-
tings greater than one.
The unity gain buffer is designed to accommodate
rail to rail input signals. The common-mode plus
signal range for the unity gain buffer amplifier is
VA- to VA+. Typical CVF (sampling) current for
the unity gain buffer amplifier is about 50 nA
(MCLK = 4.9152 MHz, see Figure 4).
The instrumentation amplifier is chopper stabilized
and operates with a chop clock frequency of
MCLK/128. The CVF (sampling) current into the
VREF+
X1
Differential
Modulator
4
th
∆Σ
Order
VREF-
X1
Digital
Filter
Sinc
5
CS5531/32/33/34-AS
Programmable
Digital Filter
Sinc
3
DS289F5
Serial
Port