CDB5534U Cirrus Logic Inc, CDB5534U Datasheet - Page 23

• Manufacturer Part Number: CDB5534U
• Description: EVAL BOARD FOR CS5534
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5534U

• Number Of Adc's: 1
• Number Of Bits: 24
• Sampling Rate (per Second): 3.84k
• Data Interface: Serial
• Inputs Per Adc: 2 Single
• Input Range: 0 ~ 2.5 V
• Power (typ) @ Conditions: 35mW @ 5 V
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS5534
• Description/function: Audio DSPs
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• For Use With/related Products: C8051F320
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1016

2.2.5. Reading/Writing On-Chip Registers
The CS5531/32/33/34’s offset, gain, configuration,
and channel-setup registers are readable and writ-
able while the conversion data register is read only.
As shown in Figure 7, to write to a particular regis-
ter the user must transmit the appropriate write
command and then follow that command by 32 bits
of data. For example, to write 0x80000000 (hexa-
decimal) to physical channel one’s gain register,
the user would first transmit the command byte
0x02 (hexadecimal) followed by the data
0x80000000 (hexadecimal). Similarly, to read a
particular register the user must transmit the appro-
priate read command and then acquire the 32 bits of
data. Once a register is written to or read from, the
serial port returns to the command mode.
In addition to accessing the internal registers one at
a time, the gain and offset registers as well as the
channel setup registers can be accessed as arrays
(i.e. the entire register set can be accessed with one
command). In the CS5531/32, there are two gain
and offset registers, and in the CS5533/34, there are
four gain and offset registers. There are four chan-
nel setup registers in all parts. As an example, to
write 0x80000000 (hexadecimal) to all four gain
registers in the CS5533, the user would transmit the
command 0x42 (hexadecimal) followed by four it-
erations of 0x80000000 (hexadecimal), (i.e. 0x42
followed
0x80000000, 0x80000000). The registers are writ-
ten to or read from in sequential order (i.e, 1, fol-
lowed by 2, 3, and 4). Once the registers are written
to or read from, the serial port returns to the com-
mand mode.
2.3. Configuration Register
To ease the architectural design and simplify the
serial interface, the configuration register is 32
long, however, only eleven of the 32 bits are used.
The following sections detail the bits in the config-
uration register.
DS289F5
by
0x80000000,
0x80000000,
2.3.1. Power Consumption
The CS5531/32/33/34 accommodate three power
consumption modes: normal, standby, and sleep.
The default mode, “normal mode”, is entered after
power
CS5531/32/33/34
35 mW. The other two modes are referred to as the
power-save modes. They power down most of the
analog portion of the chip and stop filter convolu-
tions. The power-save modes are entered whenever
the power-down (PDW) bit of the configuration
register is set to logic 1. The particular power-save
mode entered depends on state of the PSS (Power
Save Select) bit. If PSS is logic 0, the converter en-
ters the standby mode reducing the power con-
sumption to 4 mW. The standby mode leaves the
oscillator and the on-chip bias generator for the an-
alog portion of the chip active. This allows the con-
verter to quickly return to the normal mode once
PDW is set back to a logic 1. If PSS and PDW are
both set to logic 1, the sleep mode is entered reduc-
ing the consumed power to around 500 µW. Since
this sleep mode disables the oscillator, approxi-
mately a 20 ms oscillator start-up delay period is
required before returning to the normal mode. If an
external clock is used, there will be no delay. Fur-
ther note that when the chips are used in the
Gain = 1 mode, the PGIA is powered down. With
the PGIA powered down, the power consumed in
the normal power mode is reduced by approximate-
ly 1/2. Power consumption in the sleep and standby
modes is not affected by the amplifier setting.
2.3.2. System Reset Sequence
The reset system (RS) bit permits the user to per-
form a system reset. A system reset can be initiated
at any time by writing a logic 1 to the RS bit in the
configuration register. After the RS bit has been
set, the internal logic of the chip will be initialized
to a reset state. The reset valid (RV) bit is set indi-
cating that the internal logic was properly reset.
The RV bit is cleared after the configuration regis-
is
applied.
CS5531/32/33/34-AS
devices
In
typically
this
mode,
consume
the
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