CDB53L21 Cirrus Logic Inc, CDB53L21 Datasheet - Page 16

• Manufacturer Part Number: CDB53L21
• Description: BOARD EVAL FOR CS53L21 ADC
• Manufacturer: Cirrus Logic Inc

Specifications of CDB53L21

• Number Of Adc's: 2
• Number Of Bits: 24
• Sampling Rate (per Second): 96k
• Data Interface: Serial
• Inputs Per Adc: 3 Single Ended
• Input Range: ±2.5 V
• Power (typ) @ Conditions: 22.45mW @ 48kSPS, 2.5 V
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Utilized Ic / Part: CS53L21
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1550

16
3.2
Notes: 1. The
CS53L21 H/W Control
The stand-alone “CS53L21 H/W Control” switch S5 controls the Hardware Mode options of the CS53L21.
A description of each switch is outlined in the following table. See the CS53L21 Data Sheet, Section 4.2
“Hardware M
ode” for further details on setting these switches.
switch S3.
2. The
always
Header will have to be used.
I2S/LJ (Note 2.)
M/S (Note 1.)
MCLKDIV2
Switch
I2S/LJ
LJ
M/S
and is independent of this setting. If the user desires I2S format PCM SDOUT data, the I/O
These settings must be made manually by the user and have to be consistent.
setting affects the CS53L21 only and is independent of S[1] setting
setting affects the CS53L21 only. The S/PDIF Transmitter input data format in HW Mode is
Position
LO
LO
LO
HI
HI
HI
LRCK and SCLK are inputs to CS53L21.
LRCK and SCLK are outputs to CS53L21.
Internal MCLK to CS53L21 not divided.
Internal MCLK to CS53L21 divided by 2.
CS53L21 Interface Format: Left-Justified.
CS53L21 Interface Format: I²S.
Table 2. CS53L21 H/W Mode Control
Function
in the “FPGA H/W
CDB53L21
DS700DB1
Control”