CDB53L21 Cirrus Logic Inc, CDB53L21 Datasheet - Page 21

• Manufacturer Part Number: CDB53L21
• Description: BOARD EVAL FOR CS53L21 ADC
• Manufacturer: Cirrus Logic Inc

Specifications of CDB53L21

• Number Of Adc's: 2
• Number Of Bits: 24
• Sampling Rate (per Second): 96k
• Data Interface: Serial
• Inputs Per Adc: 3 Single Ended
• Input Range: ±2.5 V
• Power (typ) @ Conditions: 22.45mW @ 48kSPS, 2.5 V
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Utilized Ic / Part: CS53L21
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1550

DS700DB1
JMP
J31
J25
J28
J52
J47
J53
J14
J12
J2
J1
J3
J8
LINEB MUX
LINEA MUX
MIC2 Bias
LABEL
(AIN2B
(AIN3B
(AIN3A
Select)
Select)
Select)
VD
VD
VA
VA
VL
VL
and MIC2 bias or signal source
Selects signal source for MIC1
Selects signal source for MIC2
Selects source of voltage for
Selects source of voltage for
Selects source of voltage for
Selects signal source for the
Selects signal source for the
Selects signal source for the
bias or signal source for the
Current Measurement
Selects bias for MIC2
for the ADC input
the VD supply
the VL supply
the VA supply
PURPOSE
ADC input
ADC input
ADC I/O
ADC I/O
Table 4. Jumper Settings
*Default factory settings
POSITION
*SHUNTED 1 Ω series resistor is shorted.
*Not con-
BIAS1 to
BIAS1 to
BIAS2 to
*AIN1B
*AIN1A
*LINEB
*LINEB
*LINEA
(AIN3B
(AIN2B
(AIN3A
*+1.8V
*+1.8V
*+1.8V
Select)
Select)
Select)
AIN2A
nected
OPEN
BIAS1
BIAS2
+2.5V
+3.3V
+2.5V
+2.5V
MIC2
MIC1
MIC2
MIC2
MIC2
MIC1
Voltage source is +1.8 V regulator.
Voltage source is +2.5 V regulator.
Voltage source is +3.3 V regulator.
Voltage source is +1.8 V regulator.
Voltage source is +2.5 V regulator. .
Voltage source is +1.8 V regulator.
Voltage source is +2.5 V regulator. .
1 Ω series resistor in power supply path.
LINEB signal routed to jumper J8.
LINEB signal routed to jumper J3.
LINEA signal routed to jumper J14.
Bias on AIN2B of ADC routed to jumper J12.
Bias on AIN2B of ADC routed to MIC1.
LINEB MUX routed to AIN2B of ADC.
Bias on AIN3B of ADC routed to jumper J12.
LINEB MUX routed to AIN3B of ADC.
LINEA MUX routed to AIN3A of ADC.
Jumper placed on pin 2.
LINEB signal routed to AIN1B of ADC.
LINEA signal routed to AIN2A of ADC.
LINEA signal routed to AIN1A of ADC.
MIC2 signal routed to AIN3B of ADC.
MIC2 signal routed to AIN3A of ADC.
MIC1 signal routed to AIN3A of ADC.
J3 (for Bias on AIN2B of ADC) routed to MIC2.
J8 (for Bias on AIN3B of ADC) routed to MIC2.
FUNCTION SELECTED
CDB53L21
21