ATTINY48-MU Atmel, ATTINY48-MU Datasheet - Page 154
ATTINY48-MU
Manufacturer Part Number
ATTINY48-MU
Description
MCU AVR 4K ISP FLASH 1.8V 32-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY48-MU
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Processor Series
ATTINY4x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
2-Wire, I2S, SPI
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
24
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
32QFN EP
Device Core
AVR
Family Name
ATtiny
Maximum Speed
12 MHz
Operating Supply Voltage
2.5|3.3|5 V
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Price
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15.8.6
15.9
154
Multi-master Systems and Arbitration
ATtiny48/88
Combining Several TWI Modes
In some cases, several TWI modes must be combined in order to complete the desired action.
Consider for example reading data from a serial EEPROM. Typically, such a transfer involves
the following steps:
Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct
the Slave what location it wants to read, requiring the use of the MT mode. Subsequently, data
must be read from the Slave, implying the use of the MR mode. Thus, the transfer direction must
be changed. The Master must keep control of the bus during all these steps, and the steps
should be carried out as an atomical operation. If this principle is violated in a multi master sys-
tem, another Master can alter the data pointer in the EEPROM between steps 2 and 3, and the
Master will read the wrong data location. Such a change in transfer direction is accomplished by
transmitting a REPEATED START between the transmission of the address byte and reception
of the data. After a REPEATED START, the Master keeps ownership of the bus. The following
figure shows the flow in this transfer.
Figure 15-19. Combining Several TWI Modes to Access a Serial EEPROM
If multiple masters are connected to the same bus, transmissions may be initiated simultane-
ously by one or more of them. The TWI standard ensures that such situations are handled in
such a way that one of the masters will be allowed to proceed with the transfer, and that no data
will be lost in the process. An example of an arbitration situation is depicted below, where two
masters are trying to transmit data to a Slave Receiver.
1. The transfer must be initiated.
2. The EEPROM must be instructed what location should be read.
3. The reading must be performed.
4. The transfer must be finished.
S
S = START
Transmitted from master to slave
SLA+W
A
Master Transmitter
ADDRESS
A
Rs = REPEATED START
Rs
Transmitted from slave to master
SLA+R
A
Master Receiver
DATA
8008G–AVR–04/11
P = STOP
A
P
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