ATTINY2313V-10MU Atmel, ATTINY2313V-10MU Datasheet - Page 28
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ATTINY2313V-10MU
Manufacturer Part Number
ATTINY2313V-10MU
Description
10MHZ MLF IND TEMP GREEN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheets
1.ATTINY2313-20MU.pdf
(226 pages)
2.ATTINY2313V-10MU.pdf
(15 pages)
3.ATTINY2313V-10SU.pdf
(20 pages)
Specifications of ATTINY2313V-10MU
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-MLF®, QFN
Processor Series
ATTINY2x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
SPI/UART/USI
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
18
Number Of Timers
2
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
For Use With
ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q2312268B
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY2313V-10MU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
128 kHz Internal
Oscillator
System Clock
Prescalar
CLKPR – Clock
Prescale Register
28
ATtiny2313
The 128 kHz Internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre-
quency is nominal at 3 V and 25°C. This clock may be selected as the system clock by
programming the CKSEL Fuses to 0110.
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in
Table
Table 11. Start-up Times for the 128 kHz Internal Oscillator
The ATtiny2313 has a system clock prescaler, and the system clock can be divided by setting
the
system clock frequency and the power consumption when the requirement for processing power
is low. This can be used with all clock source options, and it will affect the clock frequency of the
CPU and all synchronous peripherals. clk
shown in
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than
neither the clock frequency corresponding to the previous setting, nor the clock frequency corre-
sponding to the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock,
which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the
state of the prescaler - even if it were readable, and the exact time it takes to switch from one
clock division to the other cannot be exactly predicted. From the time the CLKPS values are writ-
ten, it takes between T1 + T2 and T1 + 2 * T2 before the new clock frequency is active. In this
interval, two active clock edges are produced. Here, T1 is the previous clock period, and T2 is
the period corresponding to the new prescaler setting.
To avoid unintentional changes of clock frequency, a special write procedure must be followed
to change the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in
2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is
not interrupted.
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE
bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is
Bit
Read/Write
Initial Value
SUT1..0
“CLKPR – Clock Prescale Register” on page
00
01
10
11
CLKPR to zero.
11.
Table 12 on page
Start-up Time from Power-
CLKPCE
down and Power-save
R/W
7
0
6 CK
6 CK
6 CK
R
6
–
0
29.
R
5
–
0
R
4
–
0
Additional Delay from
I/O
Reserved
14CK + 64 ms
14CK + 4 ms
, clk
CLKPS3
R/W
Reset
14CK
3
28. This feature can be used to decrease the
CPU
, and clk
CLKPS2
See Bit Description
R/W
2
FLASH
CLKPS1
R/W
Recommended Usage
BOD enabled
Fast rising power
Slowly rising power
1
are divided by a factor as
CLKPS0
R/W
0
CLKPR
2543L–AVR–08/10