PIC18LF13K50-I/P Microchip Technology, PIC18LF13K50-I/P Datasheet - Page 203
![IC PIC MCU FLASH 4KX16 20-PDIP](/photos/12/13/121303/150-20-dip_sml.jpg)
PIC18LF13K50-I/P
Manufacturer Part Number
PIC18LF13K50-I/P
Description
IC PIC MCU FLASH 4KX16 20-PDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F13K50-ISS.pdf
(420 pages)
2.PIC18F13K50-ISS.pdf
(40 pages)
3.PIC18F13K50-ISS.pdf
(10 pages)
4.PIC18F13K50-ISS.pdf
(2 pages)
5.PIC18F13K50-ISO.pdf
(414 pages)
Specifications of PIC18LF13K50-I/P
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
15
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
48MHz
No. Of Timers
4
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART, I2C, MSSP, SPI, USB
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
18
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC18F13K50-ISS PDF datasheet
- PIC18F13K50-ISS PDF datasheet #2
- PIC18F13K50-ISS PDF datasheet #3
- PIC18F13K50-ISS PDF datasheet #4
- PIC18F13K50-ISO PDF datasheet #5
- Current page: 203 of 414
- Download datasheet (4Mb)
FIGURE 16-12:
TABLE 16-8:
© 2009 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
BAUDCON ABDOVF
SPBRGH
SPBRG
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
(SCKP = 0)
(SCKP = 1)
(Interrupt)
Note:
TX/CK pin
TX/CK pin
Name
CREN bit
SREN bit
bit SREN
RCIF bit
RXREG
RX/DT
Write to
Read
pin
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
‘0’
EUSART Receive Register
EUSART Baud Rate Generator Register, High Byte
EUSART Baud Rate Generator Register, Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
CSRC
SPEN
Bit 7
—
—
—
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RCIDL
ADIE
ADIP
ADIF
Bit 6
RX9
TX9
bit 0
bit 1
DTRXP
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
PIC18F1XK50/PIC18LF1XK50
bit 2
CKTXP
INT0IE
Preliminary
CREN
SYNC
TXIE
TXIP
Bit 4
TXIF
bit 3
ADDEN
SENDB
BRG16
RABIE
SSPIF
SSPIE
SSPIP
Bit 3
bit 4
TMR0IF
CCP1IF
CCP1IE
CCP1IP
BRGH
FERR
Bit 2
—
bit 5
TMR2IE
TMR2IP
TMR2IF
INT0IF
OERR
TRMT
WUE
Bit 1
bit 6
bit 7
TMR1IF
TMR1IE
TMR1IP
ABDEN
RABIF
RX9D
TX9D
Bit 0
DS41350C-page 201
on page
Values
Reset
279
282
282
282
281
281
281
281
281
281
‘0’
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