PIC18LF13K50-I/P Microchip Technology, PIC18LF13K50-I/P Datasheet - Page 251
![IC PIC MCU FLASH 4KX16 20-PDIP](/photos/12/13/121303/150-20-dip_sml.jpg)
PIC18LF13K50-I/P
Manufacturer Part Number
PIC18LF13K50-I/P
Description
IC PIC MCU FLASH 4KX16 20-PDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F13K50-ISS.pdf
(420 pages)
2.PIC18F13K50-ISS.pdf
(40 pages)
3.PIC18F13K50-ISS.pdf
(10 pages)
4.PIC18F13K50-ISS.pdf
(2 pages)
5.PIC18F13K50-ISO.pdf
(414 pages)
Specifications of PIC18LF13K50-I/P
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
15
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
48MHz
No. Of Timers
4
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART, I2C, MSSP, SPI, USB
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
18
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC18F13K50-ISS PDF datasheet
- PIC18F13K50-ISS PDF datasheet #2
- PIC18F13K50-ISS PDF datasheet #3
- PIC18F13K50-ISS PDF datasheet #4
- PIC18F13K50-ISO PDF datasheet #5
- Current page: 251 of 414
- Download datasheet (4Mb)
22.2.2.2
The PIC18F1XK50/PIC18LF1XK50 devices have
built-in pull-up resistors designed to meet the require-
ments for low-speed and full-speed USB. The UPUEN
bit
Figure 22-1 shows the pull-ups and their control.
22.2.2.3
External pull-up may also be used. The V
used to pull up D+ or D-. The pull-up resistor must be
1.5 kΩ (±5%) as required by the USB specifications.
Figure 22-2 shows an example.
FIGURE 22-2:
© 200C Microchip Technology Inc.
Note:
Note:
Microcontroller
(UCFG<4>)
PIC
The above setting shows a typical connection
for a full-speed configuration using an on-chip
regulator and an external pull-up resistor.
The official USB specifications require that
USB devices must never source any cur-
rent onto the +5V V
cable. Additionally, USB devices must
never source any current on the D+ and D-
data lines whenever the +5V V
less than 1.17V. In order to meet this
requirement, applications which are not
purely bus powered should monitor the
V
module and the D+ or D- pull-up resistor
until V
be connected to and monitored by any 5V
tolerant I/O pin for this purpose.
®
BUS
Internal Pull-up Resistors
External Pull-up Resistors
V
USB
D+
D-
line and avoid turning on the USB
BUS
enables
is greater than 1.17V. V
EXTERNAL CIRCUITRY
1.5 kΩ
the
BUS
Controller/HUB
internal
line of the USB
USB
Host
PIC18F1XK50/PIC18LF1XK50
BUS
pin may be
BUS
pull-ups.
line is
can
Preliminary
22.2.2.4
The usage of ping-pong buffers is configured using the
PPB<1:0> bits. Refer to Section 22.4.4 “Ping-Pong
Buffering” for a complete explanation of the ping-pong
buffers.
22.2.2.5
An automatic eye pattern test can be generated by the
module when the UCFG<7> bit is set. The eye pattern
output will be observable based on module settings,
meaning that the user is first responsible for configuring
the SIE clock settings, pull-up resistor and Transceiver
mode. In addition, the module has to be enabled.
Once UTEYE is set, the module emulates a switch from
a receive to transmit state and will start transmitting a
J-K-J-K bit sequence (K-J-K-J for full speed). The
sequence will be repeated indefinitely while the Eye
Pattern Test mode is enabled.
Note that this bit should never be set while the module
is connected to an actual USB system. This Test mode
is intended for board verification to aid with USB certi-
fication tests. It is intended to show a system developer
the noise integrity of the USB signals which can be
affected by board traces, impedance mismatches and
proximity to other system components. It does not
properly test the transition from a receive to a transmit
state. Although the eye pattern is not meant to replace
the more complex USB certification test, it should aid
during first order system debugging.
Ping-Pong Buffer Configuration
Eye Pattern Test Enable
DS41350C-page 249
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