PIC18LF13K50-I/P Microchip Technology, PIC18LF13K50-I/P Datasheet - Page 284
![IC PIC MCU FLASH 4KX16 20-PDIP](/photos/12/13/121303/150-20-dip_sml.jpg)
PIC18LF13K50-I/P
Manufacturer Part Number
PIC18LF13K50-I/P
Description
IC PIC MCU FLASH 4KX16 20-PDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F13K50-ISS.pdf
(420 pages)
2.PIC18F13K50-ISS.pdf
(40 pages)
3.PIC18F13K50-ISS.pdf
(10 pages)
4.PIC18F13K50-ISS.pdf
(2 pages)
5.PIC18F13K50-ISO.pdf
(414 pages)
Specifications of PIC18LF13K50-I/P
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
15
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
48MHz
No. Of Timers
4
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART, I2C, MSSP, SPI, USB
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
18
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC18F13K50-ISS PDF datasheet
- PIC18F13K50-ISS PDF datasheet #2
- PIC18F13K50-ISS PDF datasheet #3
- PIC18F13K50-ISS PDF datasheet #4
- PIC18F13K50-ISO PDF datasheet #5
- Current page: 284 of 414
- Download datasheet (4Mb)
PIC18F1XK50/PIC18LF1XK50
TABLE 23-4:
DS41350C-page 282
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
OSCTUNE
TRISC
TRISB
TRISA
LATC
LATB
LATA
PORTC
PORTB
PORTA
ANSELH
ANSEL
IOCB
IOCA
WPUB
WPUA
SLRCON
SSPMSK
CM1CON0
CM2CON1
CM2CON0
SRCON1
SRCON0
UCON
Legend:
Note 1:
Register
2:
3:
4:
5:
(5)
u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
See Table 23-3 for Reset value for specific condition.
All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Address
F9Dh
F6Dh
F6Ch
FA2h
FA1h
FA0h
F9Fh
F9Eh
F9Bh
F95h
F94h
F93h
F8Bh
F8Ah
F89h
F82h
F81h
F80h
F7Fh
F7Eh
F7Ah
F79h
F78h
F77h
F76h
F6Fh
F6Bh
F69h
F68h
F64h
Brown-out Reset
Power-on Reset,
1111 111-
0000 000-
0000 000-
-111 1111
-000 0000
-000 0000
0000 0000
1111 1111
1111 ----
xxxx xxxx
xxxx ----
xxxx xxxx
xxxx ----
---- 1111
1111 1---
0000 ----
--00 0-00
1111 ----
--11 1---
---- -111
1111 1111
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
-0x0 000-
--11 ----
--xx ----
--xx x-xx
Preliminary
RESET Instruction,
MCLR Resets,
Stack Resets
WDT Reset,
1111 111-
0000 000-
0000 000-
-111 1111
-000 0000
-000 0000
0000 0000
1111 1111
1111 ----
uuuu uuuu
uuuu ----
uuuu uuuu
uuuu ----
---- 1111
1111 1---
0000 ----
--00 0-00
1111 ----
--11 1---
---- -111
1111 1111
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
-0x0 000-
--11 ----
--uu ----
--xx x-xx
© 2009 Microchip Technology Inc.
Wake-up via WDT
or Interrupt
uuuu uuu-
uuuu uuu-
uuuu uuu-
-uuu uuuu
-uuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu ----
uuuu uuuu
uuuu ----
uuuu uuuu
uuuu ----
---- uuuu
uuuu u---
uuuu ----
--uu u-uu
uuuu ----
--uu u---
---- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuu-
--uu ----
--uu ----
--uu u-uu
(1)
(1)
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