DSPIC33FJ32MC202-I/MM Microchip Technology, DSPIC33FJ32MC202-I/MM Datasheet - Page 196
![IC DSPIC MCU/DSP 32K 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
DSPIC33FJ32MC202-I/MM
Manufacturer Part Number
DSPIC33FJ32MC202-I/MM
Description
IC DSPIC MCU/DSP 32K 28QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32MC202-IMM.pdf
(320 pages)
2.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
3.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
4.DSPIC33FJ32MC302-ISO.pdf
(436 pages)
5.DSPIC33FJ32MC204-IPT.pdf
(304 pages)
Specifications of DSPIC33FJ32MC202-I/MM
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-QFN
Core Frequency
40MHz
Core Supply Voltage
2.75V
Embedded Interface Type
I2C, JTAG, SPI, UART
No. Of I/o's
21
Flash Memory Size
32KB
Supply Voltage Range
3V To 3.6V
Package
28QFN-S EP
Device Core
dsPIC
Family Name
dSPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
16 Bit
Number Of Programmable I/os
21
Interface Type
I2C/SPI/UART
On-chip Adc
6-chx10-bit|6-chx12-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ32MC202-I/MM
Manufacturer:
Microchip
Quantity:
1 485
Part Number:
DSPIC33FJ32MC202-I/MM
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- DSPIC33FJ32MC202-IMM PDF datasheet
- DSPIC33FJ32MC202-IMM PDF datasheet #2
- DSPIC33FJ32MC202-IMM PDF datasheet #3
- DSPIC33FJ32MC302-ISO PDF datasheet #4
- DSPIC33FJ32MC204-IPT PDF datasheet #5
- Current page: 196 of 304
- Download datasheet (3Mb)
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
REGISTER 19-2:
DS70283G-page 196
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15,13
bit 14
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7-6
UTXISEL1
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for infor-
R/W-0
R/W-0
URXISEL<1:0>
mation on enabling the UART module for transmit operation.
UTXISEL<1:0>: Transmission Interrupt Mode Selection bits
11 = Reserved; do not use
10 = Interrupt when a character is transferred to the Transmit Shift Register, and as a result, the
01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is
UTXINV: Transmit Polarity Inversion bit
If IREN = 0:
1 = UxTX Idle state is ‘0’
0 = UxTX Idle state is ‘1’
If IREN = 1:
1 = IrDA
0 = IrDA
Unimplemented: Read as ‘0’
UTXBRK: Transmit Break bit
1 = Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
0 = Sync Break transmission disabled or completed
UTXEN: Transmit Enable bit
1 = Transmit enabled, UxTX pin controlled by UARTx
0 = Transmit disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled
UTXBF: Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
TRMT: Transmit Shift Register Empty bit (read-only)
1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit Shift Register is not empty, a transmission is in progress or queued
URXISEL<1:0>: Receive Interrupt Mode Selection bits
11 = Interrupt is set on UxRSR transfer making the receive buffer full (i.e., has 4 data characters)
10 = Interrupt is set on UxRSR transfer making the receive buffer 3/4 full (i.e., has 3 data characters)
0x = Interrupt is set when any character is received and transferred from the UxRSR to the receive
UTXINV
R/W-0
R/W-0
cleared by hardware upon completion
by port
at least one character open in the transmit buffer)
transmit buffer becomes empty
operations are completed
buffer. Receive buffer has one or more characters
U
x
®
®
STA: UART
encoded UxTX Idle state is ‘1’
encoded UxTX Idle state is ‘0’
HC = Hardware cleared
W = Writable bit
‘1’ = Bit is set
UTXISEL0
ADDEN
R/W-0
R/W-0
x
STATUS AND CONTROL REGISTER
(1)
RIDLE
U-0
R-1
Preliminary
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0 HC
UTXBRK
PERR
R-0
UTXEN
R/W-0
FERR
R-0
C = Clear only bit
(1)
2009 Microchip Technology Inc.
x = Bit is unknown
UTXBF
OERR
R/C-0
R-0
URXDA
TRMT
R-1
R-0
bit 8
bit 0
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