DSPIC33FJ32MC202-I/MM Microchip Technology, DSPIC33FJ32MC202-I/MM Datasheet - Page 41
![IC DSPIC MCU/DSP 32K 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
DSPIC33FJ32MC202-I/MM
Manufacturer Part Number
DSPIC33FJ32MC202-I/MM
Description
IC DSPIC MCU/DSP 32K 28QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32MC202-IMM.pdf
(320 pages)
2.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
3.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
4.DSPIC33FJ32MC302-ISO.pdf
(436 pages)
5.DSPIC33FJ32MC204-IPT.pdf
(304 pages)
Specifications of DSPIC33FJ32MC202-I/MM
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-QFN
Core Frequency
40MHz
Core Supply Voltage
2.75V
Embedded Interface Type
I2C, JTAG, SPI, UART
No. Of I/o's
21
Flash Memory Size
32KB
Supply Voltage Range
3V To 3.6V
Package
28QFN-S EP
Device Core
dsPIC
Family Name
dSPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
16 Bit
Number Of Programmable I/os
21
Interface Type
I2C/SPI/UART
On-chip Adc
6-chx10-bit|6-chx12-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ32MC202-I/MM
Manufacturer:
Microchip
Quantity:
1 485
Part Number:
DSPIC33FJ32MC202-I/MM
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- DSPIC33FJ32MC202-IMM PDF datasheet
- DSPIC33FJ32MC202-IMM PDF datasheet #2
- DSPIC33FJ32MC202-IMM PDF datasheet #3
- DSPIC33FJ32MC302-ISO PDF datasheet #4
- DSPIC33FJ32MC204-IPT PDF datasheet #5
- Current page: 41 of 304
- Download datasheet (3Mb)
TABLE 4-10:
TABLE 4-11:
TABLE 4-12:
TABLE 4-13:
I2C1RCV
I2C1TRN
I2C1BRG
I2C1CON
I2C1STAT
I2C1ADD
I2C1MSK
Legend:
SFR Name
U1MODE
U1STA
U1TXREG
U1RXREG
U1BRG
Legend:
SPI1STAT
SPI1CON1
SPI1CON2
SPI1BUF
Legend:
QEI1CON
DFLT1CON
POS1CNT
MAX1CNT
Legend:
SFR Name
Name
Name
SFR
SFR
u = uninitialized bit, — = unimplemented, read as ‘0’
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Addr
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Addr
SFR
0240
0242
0244
0248
Addr.
SFR
0220
0222
0224
0226
0228
01E0 CNTERR
01E2
01E4
01E6
Addr
020A
020C
SFR
0200
0202
0204
0206
0208
QEI1 REGISTER MAP
I2C1 REGISTER MAP
UART1 REGISTER MAP
SPI1 REGISTER MAP
UTXISEL1
FRMEN
ACKSTAT
SPIEN
UARTEN
Bit 15
Bit 15
Bit 15
I2CEN
Bit 15
—
—
—
—
—
—
—
—
—
Bit 14
SPIFSD
UTXINV UTXISEL0
—
—
TRSTAT
Bit 14
Bit 14
Bit 14
—
—
—
—
—
—
—
—
—
—
—
QEISIDL
Bit 13
—
I2CSIDL
FRMPOL
SPISIDL
USIDL
Bit 13
Bit 13
Bit 13
—
—
—
—
—
—
—
—
—
INDEX
Bit 12
—
SCLREL
DISSCK
Bit 12
Bit 12
Bit 12
IREN
—
—
—
—
—
—
—
—
—
—
—
UPDN
Bit 11
—
UTXBRK
RTSMD
DISSDO
IPMIEN
Bit 11
Bit 11
Bit 11
—
—
—
—
—
—
—
—
—
—
Bit
10
IMV<1:0>
QEIM<2:0>
UTXEN
MODE16
Bit 10
Bit 9
Bit 10
Bit 10
A10M
—
—
—
BCL
—
—
—
—
—
—
—
CEID QEOUT
Bit 8
Maximum Count<15:0>
Position Counter<15:0>
SPI1 Transmit and Receive Buffer Register
UTXBF
UEN1
GCSTAT
Bit 9
DISSLW
Bit 9
—
—
SMP
Bit 9
—
—
—
—
—
Baud Rate Generator Prescaler
SWPAB PCDOUT TQGATE
Bit 7
UEN0
TRMT
Bit 8
ADD10
Bit 8
SMEN
CKE
Bit 8
—
—
—
—
Bit 6
WAKE
Bit 7
SSEN
IWCOL
URXISEL<1:0>
Bit 7
GCEN
Bit 7
QECK<2:0>
—
—
Bit 5
LPBACK
SPIROV
Bit 6
STREN
I2COV
Bit 6
CKP
Bit 6
—
TQCKPS<1:0>
Bit 4
Address Mask Register
MSTEN
ABAUD
ADDEN
ACKDT
Bit 5
Baud Rate Generator Register
Bit 5
Address Register
Bit 5
D_A
UART Transmit Register
—
—
UART Receive Register
Bit 3
—
URXINV
RIDLE
ACKEN
Bit 4
Bit 4
Transmit Register
Bit 4
Receive Register
—
—
POSRES TQCS UPDN_SRC 0000 0000 0000 0000
P
Bit 2
—
SPRE<2:0>
BRGH
PERR
Bit 3
RCEN
Bit 3
Bit 3
—
—
S
Bit 1
—
FERR
Bit 2
Bit 2
Bit 2
R_W
PEN
—
—
PDSEL<1:0>
Bit 0
—
FRMDLY
SPITBF
OERR
Bit 1
Bit 1
RSEN
Bit 1
RBF
PPRE<1:0>
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
URXDA
Reset State
STSEL
SPIRBF
Bit 0
Bit 0
Bit 0
SEN
TBF
—
Resets
Resets
Resets
0000
0110
xxxx
0000
0000
0000
0000
0000
0000
0000
00FF
0000
1000
0000
0000
0000
All
All
All
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